Replies to post #3097 on Advanced Micro Devices Inc (AMD)

[chipguy]

Core-Logic plus 1MB of L2-Cache on a Thorougbred-size die.
Obviously we see a hybrid-process here: Core-Logic somewhere
between 90 and 130nm and Cache well below 90 nm structures already.

Perhaps you should consider the effect of highly optimized design and layout.

The L3 cache in McKinley packs 3 MB in 175 mm2. That's less than 60 mm2
per MB. That's in a 0.18 um process. I am not sure AMD even got to 60 mm2
per MB in Opteron even though it is in a full process shrink compared to
McKinley (0.13 um vs 0.18 um). BTW, the McKinley L3 uses a highly dense
hand designed sub-block architecture that Intel claimed was denser and
had higher cell efficiency than the best commercial SRAMs.

No doubt a few readers won't be able to accept that Intel engineers came up
with a new and innovative way to do something and will continue to grope
around looking for process-based excuses and explanations.

[Dan3]

Re: Core-Logic somewhere between 90 and 130nm and Cache well below 90 nm structures already.

Banias is an 80mm2 PIII core with an extra 512k cache which takes its size up to 100mm2.

The PIII is very well balanced, efficient core. Intel was never able to get high density server manufacturers or lightweight notebook makers to buy into the P4 and they've reverted to the superior PIII core for Notebooks, Blade Servers, and other applications where power/performance is important.