BTW, the McKinley L3 uses a highly dense hand designed sub-block architecture that Intel claimed was denser and had higher cell efficiency than the best commercial SRAMs.
Chipguy re: "unless Cache is not run differently on Banias".
May I understand your posting as it implies exactly this? If yes, I would be nice if you could enlight us what that would be.
For the rest, I consider efficient Chip manufactoring as when Design and process-engineering "go together like a horse and carriage." So my statement "Intel ahead in shrinks" implies any shrink is (far) more than process-engineering only. (Which you might know).
the McKinley L3 uses a highly dense hand designed sub-block architecture that Intel claimed was denser and had higher cell efficiency than the best commercial SRAMs.
No doubt a few readers won't be able to accept that Intel engineers came up with a new and innovative way to do something and will continue to grope around looking for process-based excuses and explanations.
Intel spent close to $4 Billion on R&D last year - an order of magnitude more than AMD. I suspect that Intel came up with a lot more good stuff than just one cache design - they better have, for that money.
chipguy, it's not all that impressive. If you scale it up, Tbred's L2 cache is 54mm^2 per 1MB(actual is 13.54mm^2 per 256KB). Opteron's is another story. I'll agree there's something odd about it, as I've already posted below. Paul
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