Advanced Micro Devices Inc (AMD)

[kpf]

Cache density and process roundup

of Banias is even more impressive: Core-Logic plus 1MB of L2-Cache on a Thorougbred-size die.
Obviously we see a hybrid-process here: Core-Logic somewhere between 90 and 130nm and Cache well below 90 nm structures already. (Sigh, we all are aware Intel is well ahead in shrinks, arent we?)

As for the (huge) difference of Bulk vs SoI Cache densities at AMD, this might result from two just basic considerations:
1. Learning Curve: AMD already scaled down on it more for their bulk-process than for their SoI-process.
2. Priorities: Comparing the volumes of K7 and K8 products, it makes perfect sense to focus on Cache-density of K7 first.
K8 is just in its earlier stages/steppings with little volume, not necessary to adress diesize-considerations now, just make sure the process works flawlessly.

Combining all of the above and put it into historical frames, we can expect from AMD about what Intel achieved in bulk for Banias in a couple of months (which I believe is what Thornton really is) - unless the Cache is not run differently on Banias.
For SoI we cannot conclude as easy as that. As far as cache density is concerned, we can only hope that AMD will be able to increase cache density before K8 comes into mainstream. As for this to happen not earlier than next year, there is still many months time to achieve progress in the matter. (The rumours indicating San Diego specified with 256KB L2-cache only would indicate it could take a while longer).

However, at the very end, I am not worried about both processes now - from what I see on the pricing side it sure looks like a very healthy bulk process. Finally....
As for SoI, as Mike found out 2MHz SKU already visible looks very promising.

Sure looks Bill Siegle and his team did an excellent job within the recent months catching up the gap of last year at an impressive pace. Finally...

K.