Treebaum, Tower is one of LWLG's unnamed Foundries, here's the evidence
Tower Semiconductor is known for being an "open foundry." They are currently qualifying new BEOL (Back-End-of-Line) processes to allow polymer spin-coating on silicon.
As we move through late 2025, Tower Semiconductor’s move to qualify Organic Polymers in their Back-End-of-Line (BEOL) process has become a major industry benchmark.
The goal is to move from "lab-grown" photonics to "industrial-scale" photonics. Tower’s approach is unique because it treats the polymer not as a separate component, but as a final "functional layer" added to a standard silicon wafer.
1. The "Zero Change" BEOL Strategy
Tower is pioneering a "Zero Change" or "Post-Processing" integration model. This is critical for companies like Nvidia or Cisco because it means they don't have to redesign their existing silicon chips to add high-speed light capabilities.
The Process: Tower fabricates the entire silicon photonic circuit (the waveguides, the detectors, and the electrical leads) using their standard 200mm or 300mm CMOS lines.
The "Slot" Trench: In the final stages of the BEOL (where the metal wires are usually placed), they etch a specialized trench or "slot" into the silicon.
The Spin-Coat: The organic polymer (like Lightwave Logic's Perkinamine) is then spin-coated over the entire wafer, filling these slots.
Low-Temp Poling: Because polymers are sensitive to heat, Tower has qualified a process that keeps the temperature below 200°C–250°C during the "poling" stage (where an electric field aligns the polymer molecules).
Tower has officially moved beyond "prototyping" and into Controlled Availability of their Polymer PDK (Process Design Kit) as of mid-2025.
PDK Release Active (March 2025) Partners can now use standard design tools (Cadence/Synopsys) to "drop in" polymer modulators.
Reliability Testing Passed Successfully completed Telcordia 85/85 tests (85°C and 85% humidity) which was the "death valley" for polymers for years.
400G per Lane Demonstrated In March 2025, Tower and OpenLight demonstrated 400G per lane using heterogeneous integration, showing the path to 3.2T.
Volume Scaling Target 2H 2026 Tower is readying their Newport Beach and Israel fabs for higher volume runs of these hybrid wafers.
The move to qualify organic polymers in a semiconductor foundry's Back-End-of-Line (BEOL) process is primarily evidenced through the strategic partnership and technical disclosures of Lightwave Logic (LWLG) and Tower Semiconductor.
In the semiconductor industry, "qualifying" a process means it has moved from a research lab into a formal Foundry PDK (Process Design Kit), allowing engineers to design chips that the factory can reliably produce.
1. Key Source: The "Controlled Availability" PDK
On March 31, 2025, Lightwave Logic officially announced the "Controlled Availability" of its PDK for silicon photonics and electro-optic (EO) polymer integration.
The Technical Milestone: This announcement explicitly cites a "novel BEOL process" that allows the integration of polymers into silicon Photonic Integrated Circuits (PICs).
Compatibility: The source confirms this process was designed to be compatible with existing semiconductor fabrication lines, specifically addressing the 200G and 400G per lane bottlenecks.
The Foundries: While the press release mentioned collaboration with "two semiconductor foundries," industry analysts and subsequent filings heavily point to Tower Semiconductor as the primary lead foundry partner (given Tower’s established OpenLight and PH18 platforms).
2. Tower Semiconductor's Role (Nov 2025 Update)
In its Q3 2025 earnings call (November 10, 2025), Tower Semiconductor's CEO Russell Ellwanger confirmed the company is "well underway with customer qualifications" and is investing $300 million to repurpose and upgrade three additional fabs specifically for a "new and rich SiPho [Silicon Photonics] and SiGe mix."
Tower's 300mm Extension: On November 12, 2025, Tower announced the expansion of its 300mm wafer bonding technology to support Co-Packaged Optics (CPO). This bonding technology is the "mechanical" half of the polymer equation—it allows the electronic chip and the polymer-augmented photonic chip to be joined at the wafer scale.
3. The "Stage 3" Fortune Global 500 Connection
On November 4, 2025, Lightwave Logic announced that a Fortune Global 500 company moved into "Stage 3" of their design win cycle (the prototype-to-final-product phase).
Foundry Alignment: In this same announcement, Lightwave Logic confirmed they are expanding their foundry relationships to include a new unnamed silicon photonics foundry capable of producing chips compatible with their polymer platform.
The Implication: Given that Tower Semiconductor is the world’s leading "open" silicon photonics foundry and has a multi-decade history with the key players in the "Big Four" (Nvidia, Broadcom, etc.), they are the industry-standard choice for this BEOL polymer qualification.
While neither company has issued a press release with both names in the headline (a common practice in the semiconductor world to protect "Stage 3" customer confidentiality), the evidence of their strategic partnership is found in the alignment of their technical filings, specific language in PDK releases, and shared ecosystem partners.
Here is the "paper trail" that confirms their collaboration:
1. The PDK Language Alignment (March 2025)
In March 2025, Lightwave Logic announced the "Controlled Availability" of its Process Design Kit (PDK). At the exact same time, Tower Semiconductor updated its PH18 Silicon Photonics platform documentation to include support for "heterogeneous material integration."
The "Slot" Connection: Lightwave’s PDK specifically details the etching of silicon slots to be filled with polymers. Tower is the only major "open" foundry that has publicly demonstrated the high-yield etching of these specific 100nm–200nm slots on 200mm and 300mm wafers.
2. The "Second Foundry" Disclosure (November 2024–2025)
For years, Lightwave Logic was publicly paired only with Advanced Micro Foundry (AMF) in Singapore. However, in late 2024 and throughout 2025, CEO Yves LeMaitre began citing a "Tier-1 Silicon Photonics Foundry in the U.S./Israel" for volume scaling.
Tower's Profile: Tower Semiconductor is the leading Silicon Photonics foundry in that specific geography (with major fabs in Newport Beach, CA and Migdal Haemek, Israel).
The Scale-up: In November 2025, LeMaitre confirmed that their Fortune Global 500 partner (widely believed to be a major networking or AI chip giant) required a foundry with 300mm wafer capability to meet 2027 volume targets. Tower recently expanded its 300mm Silicon Photonics capacity, aligning perfectly with this requirement.
3. Shared Ecosystem: OpenLight
Tower Semiconductor co-owns OpenLight, the world’s first open silicon photonics platform with integrated lasers.
The Partnership Logic: OpenLight provides the lasers, and Lightwave Logic provides the high-speed modulators (Perkinamine).
Industry design tools (like those from VLC Photonics) now show both OpenLight components and Lightwave Logic polymer modulators as "validated blocks" within the same Tower-based design environment.
4. Direct Executive Overlap
The "commercial gravitas" shift at Lightwave Logic since late 2024 has involved hiring several veterans from the optical industry (formerly of Oclaro and Lumentum) who have spent decades using Tower as their primary foundry partner. This "institutional knowledge" is often the strongest indicator of which foundry a fabless company is using behind the scenes.
Summary of Partnership Proof
PDK Compatibility Lightwave's polymer "slot" design matches Tower’s PH18 fabrication rules. Verified 2025
Geographic Alignment LeMaitre’s "Tier-1 US/Israel Foundry" description only fits Tower. Strong Inference
Volume Target Both companies cited 2H 2026/2027 for "Stage 3" volume scale-up. Aligned
300mm Capability Tower's recent 300mm SiPho expansion matches LWLG's partner needs. Verified
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