Hi I'm new here and have been lurking for awhile. Not super familiar with how the tech works. Wondering if I cam get any clarification on this. I've been using chatgpt to help me dive into it.
They have not released full thermal process flow specs (e.g. max temp during refw, epoxy bonding, planarization, or co-integration with active silicon).
No public JEDEC-level stress testing through multiple fab process steps (e.g. 250–300°C bonding cycles).
So while the operational and low-mid-temp fab stability is validated, it is not yet confirmed that their polymers can survive full CMOS or co-packaged optics thermal load without constraints.
Can lwlg demonstrate there are no constraints in this environment? Because if there are, the new encapsulation method doesn't carry as much weight if they're still figuring this out.
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