Lightwave Logic Inc (LWLG)

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Process design kit

From Wikipedia, the free encyclopedia

A process design kit (PDK) is a set of files used within the semiconductor industry to model a fabrication process for the design tools used to design an integrated circuit. The PDK is created by the foundry defining a certain technology variation for their processes. It is then passed to their customers to use in the design process. The customers may enhance the PDK, tailoring it to their specific design styles and markets. The designers use the PDK to design, simulate, draw and verify the design before handing the design back to the foundry to produce chips. The data in the PDK is specific to the foundry's process variation and is chosen early in the design process, influenced by the market requirements for the chip. An accurate PDK will increase the chances of first-pass successful silicon.

Description

Different tools in the design flow have different input formats for the PDK data. The PDK engineers have to decide which tools they will support in the design flows and create the libraries and rule sets which support those flows.

A typical PDK contains:

A primitive device library
-Symbols
-Device parameters
-PCells

Verification checks
-Design Rule Checking
-Layout Versus Schematic
-Antenna and Electrical rule check
-Physical Extraction

echnology data
-Layers, layer names, layer/purpose pairs
-Colors, fills and display attributes
-Process constraints
-Electrical rules

Rule files
-LEF
-Tool dependent rule formats

Simulation models of primitive devices (SPICE or SPICE derivatives)
Transistors (typically SPICE)
-Capacitors
-Resistors
-Inductors

Design Rule Manual
-A user friendly representation of the process requirements

A PDK may also include standard cell libraries from the foundry, a library vendor or developed internally

-LEF format of abstracted layout data
-Symbols
-Library (.lib) files
-GDSII layout data

Original article below, with link and further resources:
https://en.wikipedia.org/wiki/Process_design_kit

Note tht the discussion below idoes not cover a bleeding edge new polymer -

sonicSkis
•
5y ago
•
EE - PhD
Analog/Mixed System chip designer here. This is a great answer. To give some perspective, it can take 1-2 years to do the chip design, so the fab time may or may not be a significant chunk of the whole program schedule. Either way, the time after tapeout is usually needed for vacation (for the burned out design team) and to bring up the test and SW for the chip.

https://www.reddit.com/r/AskEngineers/comments/fx6wc9/how_long_does_it_take_from_the_time_a_cpus_design/