Register for free to join our community of investors and share your ideas. You will also get access to streaming quotes, interactive charts, trades, portfolio, live options flow and more tools.
Register for free to join our community of investors and share your ideas. You will also get access to streaming quotes, interactive charts, trades, portfolio, live options flow and more tools.
The L1 latency has always been 4 cycles in Intel's non-Netburst x86 architectures. I know RWT said it was increased from 3 to 4, but that info is wrong, as far as I know. If there was another source that claimed this, I'd like to see it.
The term "4-cycle load loop" lives in infamy among designers on Nehalem, Penryn, Merom, and every P6 derivative. Many are the engineers that have tackled the mountain that is the 4-cycle load loop despite ever-shrinking clock cycles and ever-increasing RC delays. I can attest that those battles have left many engineers scarred and bloodied (though ultimately victorious).
As for L3 latency, it is useless to speculate on one small part of a memory subsystem that has been completely revamped from the L1 all the way up to system memory. But of course, we all know that you will assume the worst...
Good eye. You've identified one of the key new principles of the Nehalem design. I've heard that there was a lot of tension and controversy during the architectural definition phase of the design due to this constraint; it was a hard pill for some to swallow. I believe there were even one or two Merom uarch features that were removed because the perf/power tradeoff was too far off from this standard.
The early specs I saw, dated around 2003 I think, showed the L2 cache in each core being 512K (thus my hints that 256K was incorrect). That apparently changed somewhere along the way, and I suspect (but can't say for sure) that this 1/3 perf/power ratio played a part in that. That should teach people to not listen to my not-so-subtle hints (probably a good idea anyway).
There is no "cache size issue". Savantu is clueless.
The key point that has been missing is that the L2 cache in each core is inclusive of the shared 8MB L3, which means that a portion of the large shared cache is available to each core for very, very fast access. I actually think it would be more technically accurate to refer to Nehalem's L3 as an L2 just like Penryn, but refer to the 256K cache in each core as a "L1.5" cache, which can get you data from that shared cache that much quicker.
Didn't even need to click on it to know that was written by Anders Bylund. Huge AMD honk at the fool, and has held AMD shares all the way from their peak. What a joke...
Ya know, looking at that die photo again, I'm surprised that Hans is sticking to his 256k L2 size estimate. That sure doesn't look like 1/8th the size of the 2MB chunk of L3 to me. Looks more like 1/4 the size. Doesn't it?
If you take the 4-core Nehalem die slide we've been talking about, and turn it 90 degrees, it looks to me like the capacitors on that package align perfectly to the 4-core die pattern...
My guess is the beefier capacitors on the left are for the DDR3 drivers...
Intel's CEO publicly presented a slide showing a 4-core Nehalem die, with a clear label that says, "3 Ch DDR3".
You're thinking too much...
This slide still has a few inaccuracies (one of which you have correctly pointed out). He has corrected a couple things since the last version I saw from him, but it still looks to be nothing better than his best educated guess as to the die specifics...
In terms of margins, I think Intel made their goal for Silverthorne and follow-ons pretty clear in the last slide:
GOAL: TAM Expansion at Company Average Margins
Ya know, I've been wondering what kind of performance impact hyperthreading might have on Silverthorne.
I know there's been some skepticism about performance due to the processor being an in-order design, but at first blush it seems like an in-order pipeline would get more of an incremental benefit from multi-threading than an out-of-order design. I wonder if the Intel architects found through their simulations that HT has a higher ROI in terms of ILP than adding the OOO overhead. Of course, the downside is you need OS and application support, but x86 has been doing the heavy lifting there for the last 5-7 years.
I know this is just one benchmark, but the improvement with HT enabled looks pretty remarkable...
Speaking of youtube, it looks like Intel has put up their latest TV ad:
Is it possible the EU raids yesterday could be a positive indicator of Intel's chances in their case?
The timing strikes me as odd. Consider that the EU already issued their formal complaint, and Intel already issued their formal response. All that's left is a hearing.
What this raid tells me is that Intel's response may have provided enough of a defense that the EU doesn't consider their case strong enough as-is, and they feel a need to dig even deeper in unexplored areas (retail, supply chain) if they hope to find dirt.
Probably a pipe dream, but hope springs eternal. I'm still fearing the worst, but consider this a potentially positive development for Intel...
FYI, the cache size info in that screenshot isn't correct either.
You are wrong. The Nehalem design team has been based in Oregon from day one, and is named after the Nehalem river that flows through the Oregon coastal range.
Don't believe everything you read on Wikipedia...
You're piling assumptions on top of assumptions.
You assume the reported cache sizes are accurate (they're not).
You assume that you know more than Intel architects (you don't).
You assume that analyzing the high-level, complex, qualitative relationship between frequency, power, and future scaling is a comparable problem to the easily simulated, quantitive problem of a cache hierarchy's affect on performance (it's not).
I'll give you that the screenshot capture raises interesting questions about Nehalem, but since the intro is still at least 6-9 months out, the only prudent thing to do is make note of them, and wait and see to find out what the truth is. Any further alarmist prognostications is the height of arrogance, and thoroughly trollish behavior...
Nice link. My favorite part:
"In session 10.2 at IEDM 2007, Intel presented a paper titled A 45 nm Logic Technology with High-K+ Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193 nm Dry Patterning and 100% Pb-free Packaging [4]. In this paper, Intel presented details on its 45 nm process technology that, on paper, could not be matched by any other 45 nm process technology presented at IEDM in 2005, 2006 or 2007. Aside from the achievement of successfully integrating Metal gate-electrode, (High-K) Hafnium-based gate-dielectric, and the use of dry 193-nm lithography, Intel also managed to achieve record NFET and PFET drive currents - 1360/1070 uA/um at 100 nA/um Ioff and 1.0V Vdd – that were not matched by other 45 nm process technologies thus far presented at IEDM. In particular, the impressive 51% improvements in PFET drive current from its 65 nm process technology should enable Intel to continue to enjoy the triple crown of smaller die size, faster and lower power circuits for designs that are ported to the 45 nm and specifically accounts for the shift in relative NFET and PFET drive current improvements.
Overall, Intel’s 45 nm process technology appears to be an enormously impressive technology that should enable it to continue its role as the dominant semiconductor manufacturer of the present time."
Isn't 400,000 quad-core shipments surprisingly high?
My prediction: Ruiz is going to go 'scorched earth' today, and blame AMD's problems on a worldwide slowdown in semiconductors, and warn of a global recession. The analysts will eat this up, because it's what they've been waiting to hear from somebody, and Hector will tell them exactly what they want to hear so attention is diverted from AMD's screwups. It's not like AMD stock isn't already in the toilet.
This will cause the market to continue eroding, and INTC will get slammed again for at least a buck a share.
Man, I need to cheer up...
Thread,
This market is really screwed up. Doesn't anybody here own other stocks? The last 3-6 months have been absolutely brutal to several stocks I either own or follow, and every time the reaction has been the same: What the hell is the market thinking? Are they stupid? The internet is currently littered with message boards like this one, filled with folks who are CONVINCED that the market has it completely wrong.
The first few stocks this happened to, I made the plunge and bought some shares at what I thought were bargain prices. In every single case, they have gone further south (in some cases, significantly).
I have taken solace in the fact that my largest investment, INTC, avoided these market doldrums last quarter. But when it suddenly dropped to 22 last week, and everybody here was buying shares and calls, I had a bad feeling. Today's AH drop tells me that INTC isn't immune from this apparent desire of folks to dump their stocks.
No, I am not selling my shares. I've held them this long, I can hold them some more. But I ain't buying either. Folks here may find it hard to believe that INTC could go lower than the $17 lows we saw in 2005 and early 2006, but from what I'm seeing elsewhere, that would simply be par for the course.
This market is just screwed up. Buyer beware...
Andy Grove battling Parkinsons:
http://www.forbes.com/free_forbes/2008/0128/070.html?partner=yahoomag
Sarmad,
I think this person has a point. Go back to techno_bull's original post, and click on that link. I think the headline is wrong, and should indeed read Q4, 2006. Here is the first paragraph:
"Banc of America Securities said it raised its earnings estimates on chipmaker Intel Corp. (INTC.O: Quote, Profile, Research) to 27 cents a share from 26 cents for the fourth quarter and to $1.27 a share from $1.25 for 2007."
First of all, there is no way that any analyst could currently have a Q407 estimate of only $0.26, and raise it to only $0.27. I think the lowest estimates out there are for EPS of $0.35. Consensus is around $0.40.
Second of all, the full-year estimate for 2007 is phrased in a way that implies a full-year estimate for next year. I have seen several sell-side reports that include an estimate for this Q4, immediately followed by an estimate for 2008 (most of which are in the $1.50-$1.60 range).
And finally, the article is indeed dated Jan. 4th, 2007. I think the headline is wrong, and nothing should be read into this year-old article.
I'm also holding off on pulling the trigger. The current market and macroeconomic conditions have made for very, very sharp falling knives lately, and every time I've bought my other stocks on the dip this fall, I've regretted it. Intel has been extremely resilient in this market, in fact I've been amazed how resilient it's been. But a 15% drop in 2 days (which is nothing compared to some other stocks I've been following) leaves me wondering if now is simply it's time...
My trigger finger will start getting itchy below 20, and then only after a stable or upward trend. Until then, I'm content to wait out any market gyrations with my relatively large (for me) share holdings.
Personally, I am eagerly awaiting to see if Intel's marketing does anything special in emphasizing Nehalem's Turbo Mode to differentiate this product from anything else that is out there.
I think this feature has the potential to spur much more quad-core demand on the desktop, and significantly raise ASPs.
Think about it - By spending more for a quad-core Nehalem, you are getting two bonuses for your money: extra performance now through higher frequency on single-threaded apps, and significantly higher performance later as more and more multi-threaded applications and games come online.
It's currently a hard sell for anything greater than 2 cores, because most folks know they won't get anything for their extra money; who needs 4 cores right now on the desktop? But with Nehalem, they will at least get a frequency/performance boost, and it might make that sell a little easier since they will be getting some tangible add-on value.
They could even go so far as to provide two frequency ratings, something like:
4C-2.8GHz/2C-3.4GHz
(btw these numbers are made up, I have no idea what Nehalem frequencies will look like).
What if you were to insert mid-range quad-core parts at the top of the price stack alongside the top-bin dual-core parts? As a very rough example, something like this:
$1299 -- 4C top-bin
$999 -- 4C bin-1
$699 2C top-bin 4C bin-2
$499 2C bin-1 4C bin-3
$299 2C bin-2
Heh, that's why I'm a CPU innards guy and not a system guy. I (obviously) know nothing about PCIe, and only know enough about CSI to be dangerous. Thanks for the correction, you're right, PCIe is indeed point-to-point. So other than pointing out the peak bandwidth differences, I will simply plead ignorance on any comparisons between PCIe and CSI...
You misunderstood my first questions.
Sorry, the first question was worded strangely...
Are there any other issues apart for Bandwidth and Latency, which makes PCIe unsuited for processor to processor interconnect ?
<Shrug> I really have no idea. I honestly don't know much about PCIe. Off the top of my head, I would guess that PCIe isn't a point-to-point architecture, and thus not amenable to what the system architects were trying to achieve. I would also observe that "apart from Bandwidth and Latency" doesn't leave much else that matters...
Finally, Intel wanted to create an architecture that could live on and be scalable for the next 10+ years in all segments of the workstation and server market, for both x86 and IPF. Something based off PCIe would seem to be more of a stopgap.
Nehalem is just the tip of the Quickpath iceburg...
A. Why was the performance gain to justify the development of CSI ?
Because the bandwidth scales with multiple sockets in a CSI system. The FSB has a fixed bandwidth, and if you put 4 CPUs on it, then they all have to share that bandwidth, creating saturation and making the actual bandwidth of each core much less than the theoretical maximum.
CSI, on the other hand, is a point-2-point protocol that provides a dedicated link between each socket, so if you have a max bandwidth of 32GB/s, then you can potentially achieve that bandwidth between each core, even with 4 sockets.
Note that comparing raw bandwidth numbers between FSB and CSI is kind of apples-to-oranges, because CSI has multiple links all operating at that bandwidth. If one were to assume that 4 CSI links were connecting 4 CPU sockets, and each one was operating at its maximum 32GB/s, then one could argue that the total system bandwidth at that point was 128GB/s. But that's a far-fetched assumption that all links would be going full-bore for any significant amount of time...
B. If CSI is that good, why is not being used to connect the GPU and the processor ?
You answered your own question by pointing out the large installed base of PCIe graphics cards. Maybe someday CSI could be used for other system components like this, but I doubt it would be anytime soon.
C. Is CSI limited to board level interconnect only?
Theoretically, no. The CSI architects took a page from the network guys and divided the spec into distinct layers. The protocol layer is separate from the link layer, which is separate from the physical layer (think of something like a tcp/ip stack). Theoretically, the physical layer could be any possible way you could conceive of to send and receive 20 bits of data, including fiber-optic, wireless, etc.
Note that the bandwidth will be a function of this physical implementation; the high bandwidth numbers being quoted here are because the bus is being implemented with differential-pairs that can switch very quickly, and with an asynchronous clock that allows for a large data-capture window. Other physical mediums may require longer or shorter switching frequencies...
Actually, I think the number of clock & data bits per link is 84 bits (20 data + 1 clock, both directions, differential pairs). Unless there are two clocks per directional link? I thought there was only one.
Another thing that really helps board layout is that the CSI spec allows for dynamic configuration of the bus, allowing the physical bit order to be reversed. So you could connect bit 0 of one agent to bit 19 of another agent, bit 1 to bit 18, bit 2 to bit 17, etc, and the CSI agent should automatically detect this and reconfigure itself appropriately. This should give board makers a lot of flexibility...
I think comparing Quickpath to PCI-e is asking the wrong question.
For one thing, Quickpath was never meant to replace PCIe, it was meant to replace the FSB, whose bandwidth does not scale with multiple cores.
What's clouding the picture is that the system bus in single-socket systems will be going away soon, as more and more gets integrated into the CPU socket (I often hear nowadays the CPU socket being referred to as a system 'black hole', continually sucking more and more components into it).
Currently, there are two hops from the GPU to the CPU:
Today: GPU --(PCIe)--> chipset --(FSB)--> CPU
According to the slides that wbmw linked to, the first Nehalem implememtation will replace the FSB with Quickpath:
Bloomfield: GPU --(PCIe)--> chipset --(Quickpath)--> CPU
Then with Lynnfield, one hop is being completely eliminated, so all that is left is a direct link between the CPU and GPU:
Lynnfield: GPU --(PCIe)--> CPU
The question you should be asking is this: How much will integrating this chipset functionality into the CPU (and thus removing one of these hops altogether) improve overall system performance?
I have no idea, but I'm anxious to find out...
Remember, Quickpath was meant for multiple-socket systems, and really shines in that space. We may see some computer makers offer initial single-socket Nehalem systems with one Quickpath link, but that will only be a stopgap until Intel can release Lynnfield (which eliminates the system bus altogether).
In two years, I expect to see two general system architectures from Intel that are fully optimized for their markets:
1) For mobile and desktop: Single-socket CPU/chipset with either a direct link to a GPU, or with a GPU also integrated into the CPU socket.
2) For servers/workstations: Multiple-socket CPUs with direct Quickpath links to all other CPUs and the chipset. Bandwidth galore.
That's how I see things playing out, anyway...
I appreciate the takes on turnover in the India high-tech industry. I consider this especially relevent to Intel, since Intel has a processor design team in Bangalore as well. I believe they focus on high-end server products (>4 cores, >4 sockets, etc).
I have to wonder if AMD will be opportunistically gunning for some inside IP. Maybe it won't take them very long to ramp up their new design team after all...
I'll be looking for their announcement in Penang, Malaysia, next. (Only half joking).
Well, I finally got stopped out of my AMD puts this morning. I had decided I wanted to sell them for an ~80% gain when the stock price dipped below $12, but submitted a stop-limit order in case it fell further. I'm glad I did! The final sale price gave me a 141% gain before commissions. It was a very tiny position, but even this small bet helped significantly stem the losses in my overall portfolio these last few weeks. Now I'm on the hunt for some bargains with my new-found cash. Anybody have a favorite? (besides INTC)
I can't explain why, I just know that I'm loving it, as my tiny number of AMD puts are doing a decent job of stemming the losses in my overall portfolio. If I ever get stopped out of these puts (I keep moving the stop price up, up, up), then I will have a nice chunk of change to go bargain-hunting. Thank you AMD!
I think the horrific Phenom launch yesterday (I haven't seen such a widely panned technology introduction in a long time) provided a catalyst for portfolio managers to do EOY house-cleaning and take some tax losses. The whole "just wait until XXXX product" argument just ran out of gas, since there are no future products left to hang your hat on, and everybody can finally realize that with AMD, what you see is what you get.
I just wish Intel wasn't getting dragged down, too. Time to dip into some INTC calls, perhaps?
AMD getting hammered today, and briefly dipped below its 52-week low. The arabs' investment is already down by $60 million. Poor guys...
Does AMD really not have support for microcode patching?
Wow, that's technology that was in the P6 in the mid-90s. Surely AMD has something similar?
This is one of the most asinine arguments I've ever read on this board.
No, Intel has not explicitly provided details behind the design of Silverthorne. Nor do they for any product. Everybody knows that Silverthorne is a brand-new, from-the-ground-up design. Except you. I wonder why that is?
You know, Intel has never explicitly stated that Itanium is a separate design from Xeon. You might be on to something here....
Sheesh!
Of course this is a brand new design. What do you think all those folks in Austin were doing after Tejas got cancelled?
Here's your answer:
http://www.intel.com/community/texas/spotlight.htm
Saturn, all you need to remember is that a DP Nehalem will have 2 CSI links (can communicate directly with the other processor and the chipset), while a MP Nehalem will have 4 CSI links (can communicate directly with 3 other processors plus the chipset). These are, indeed, different chips, and have different projects associated with them (DP is Bloomfield, I think, while MP is Beckton). The number of cores per socket is almost irrelevant to this discussion (notice the slides say 'up to' 8 cores); what's important is how many CSI links there are per socket.
If you look at the diagram for the 8-socket system, you'll notice that each socket still only has 4 CSI links. However the difference is that each socket no longer has a one-shot link to every other component; now a "hop" is required in some cases to get data from one component to another. This is an additional layer of complexity in the CSI logic, which is accounted for in the CSI spec, but you can bet that Intel will be focusing on the 'easy' things first like 2S and 4S systems.
The Nehalem demo at IDF was a 2-socket system, so logic would dictate it has 2 CSI links, and will likely be the first Nehalem product. Alan's assumption of an MP Beckton in 2009 seems reasonable to me...
Beamer, I think you're buying a little too much into the never-ending story from AMD apologists.
I'm with you on AMD's probable financial success in Q4. Their Q3 results were surprising, and bodes well for sniffing profitability soon.
But I disagree on the effect that will have on their stock price. I think the current level of $14-$15 is based entirely on high expectations of break-even in Q4, and I don't think doing so will send it much higher.
As for Q1, I think all the additional 45nm capacity that Intel will be bringing online will put much more pressure on AMD than they felt in Q3 or will feel in Q4. Combined with normal seasonality, I think the possibility exists for another Q1 warning like we saw this year.
I bought long-term 09 puts for a reason, and I plan to hold through Q1 for better or worse (though it's a very small number of contracts). I do admit that the general market behavior on Friday is playing a role in my thinking as well, as AMD puts tend to be my favorite way to hold a small hedge against a market meltdown.
Should be interesting to watch it all unfold, at any rate...
Looks like this is a classic case of a rising tide lifting all boats. Very strong PC and microprocessor market, and both Intel and AMD are benefitting.
I would also point out that AMD is benefitting this quarter from what Intel will benefit from next quarter: since Barc got qual'd for production, then everything related to it got moved from COGS to inventory. COGS affects GM, inventory doesn't. I think this contributes to Intel's expected big jump in GMs next quarter.
I knew I should have stayed away from the AMD put well through Q3 and Q4. Oh well, that's why I gambled just a fraction of what I did during last summer's swoon. At least they're 09 puts, so anything could happen still...
Looks like AMD sold all remaining shares in Spansion ($326M worth) to keep their cash balance unchanged from Q2 at $1.5B.
Their solvency is probably assured through next year at this point, but they're running out of things to sell to keep them afloat...
The sequential revenue growth and margin improvement is impressive, but the higher loss will probably get the headlines. Probably little change in the share price tomorrow...
AMD suddenly jumped up to $14.50 in the last 20 minutes. Either somebody's gambling, or somebody knows something...