Intel Corp (INTC)

[ChipGeek]

The L1 latency has always been 4 cycles in Intel's non-Netburst x86 architectures. I know RWT said it was increased from 3 to 4, but that info is wrong, as far as I know. If there was another source that claimed this, I'd like to see it.

The term "4-cycle load loop" lives in infamy among designers on Nehalem, Penryn, Merom, and every P6 derivative. Many are the engineers that have tackled the mountain that is the 4-cycle load loop despite ever-shrinking clock cycles and ever-increasing RC delays. I can attest that those battles have left many engineers scarred and bloodied (though ultimately victorious).

As for L3 latency, it is useless to speculate on one small part of a memory subsystem that has been completely revamped from the L1 all the way up to system memory. But of course, we all know that you will assume the worst...