Intel Corp (INTC)

[ChipGeek]

Good eye. You've identified one of the key new principles of the Nehalem design. I've heard that there was a lot of tension and controversy during the architectural definition phase of the design due to this constraint; it was a hard pill for some to swallow. I believe there were even one or two Merom uarch features that were removed because the perf/power tradeoff was too far off from this standard.

The early specs I saw, dated around 2003 I think, showed the L2 cache in each core being 512K (thus my hints that 256K was incorrect). That apparently changed somewhere along the way, and I suspect (but can't say for sure) that this 1/3 perf/power ratio played a part in that. That should teach people to not listen to my not-so-subtle hints (probably a good idea anyway).