Replies to post #3297 on Advanced Micro Devices Inc (AMD)

[yourbankruptcy]

dougSF30, what you've said is exactly what wbmw said. 1. adding pipeline stages to boost the clock frequency. 2. adding pipeline stages to remove the bottleneck in decode logic.

From my point of view 2 implies 1.

[wbmw]

Doug, Re: Do you have any links to support these observations?

It might have been something from Hand deVries, it might have been something from MPF, or it might have been elsewhere. At some point, I read about the additional two pipeline stages being used to improve a bottleneck in the decode logic. Given that, there is no logical conclusion that the pipeline stages were also added to improve frequency. As you know, unless you balance your pipeline, you do not get frequency advantages. I don't necessarily think that AMD rebalanced the pipeline after adding the additional stages. Or, I should say that there is no evidence to support this (especially given the huge frequency miss at launch - I know that SOI is largely to blame, but it's hard to believe that it even misses with the advantage of a newly balanced pipeline).

Now, with this, I have been very patient with your inquisitions, especially since your tone has been less than pleasant. You treat me more like a debate opponent than someone who is trying to share knowledge on a public forum. If you don't like what I have to say, I will stop.