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Post# of 98355
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yourbankruptcy

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yourbankruptcy

Re: dougSF30 post# 3297

Monday, 04/28/2003 6:41:07 PM

Monday, April 28, 2003 6:41:07 PM

Post# of 98355
dougSF30, what you've said is exactly what wbmw said. 1. adding pipeline stages to boost the clock frequency. 2. adding pipeline stages to remove the bottleneck in decode logic.

From my point of view 2 implies 1.

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