Replies to post #127076 on Intel Corp (INTC)

[chipguy]

So, why didn't Intel optimize the metal stack for density for its low power processes?

Uh, have you not seen any presentations from Intel in the last few
years? It's coming but when 99+% of revenue and 100% of profits
come from high performance MPU processes it takes a lot of effort
from the very top down to get LP SoC process equal attention and
priority among rank and file of the product design, design support,
process tech R&D, and manufacturing groups.

[Shhh---]

They did Ashraf to the extent they could given design rule constraints.

M1 for Intel 22nm is 90nm pitch, not much smaller then TSMC
M2,M3 are 80nm pitch which is noticeably smaller

Intel's gridded design rules / 1D routing mean for a given minimum pitch they have less dense processes.
These rules also mean though that they can leverage SADP in addition to LELE. This enables smaller geometries, higher yields, and significantly less cost due to the removal of both a litho step and an etch step.

TSMC will have a hell of a time porting all of their ecosystem's IP to a gridded layout so it's an advantage Intel will likely have for the next few years. It is in my opinion the reason why intel can show an accelerating rate of cost reduction over the historical exponential trend at 14nm while the foundries are not only slowing or even flatlining in cost reduction per function, but actually predicting an increase for the first time in history.

I don't undetstand why more people aren't talking about this. It's bigger than FinFETs. When your competition can decrease costs at an exponential rate and yours are increasing you're in deep yoghurt, to say the least. Perhaps no one believes Intel can pull it off. Or perhaps the cognitive dissonance is so strong it simply isn't registering...