Intel's gridded design rules / 1D routing mean for a given minimum pitch they have less dense processes. These rules also mean though that they can leverage SADP in addition to LELE. This enables smaller geometries, higher yields, and significantly less cost due to the removal of both a litho step and an etch step.
.....all designs are based on a grid..........at least they were when I retired 14 years ago. What's different about TSMC? Does not TSMC already use double patterning? So Intel uses SADP and TSMC uses LELE. Is that your claim? Doesn't SADP also require a second etch. Seems as though a sidewall image built on a mandril would be a continuous feature and would require trimming? No? Explain how Intel avoids this. Explain in a bit more detail what inherent advantage Intel has at say 14nm that TSMC does not. I mean....it's not like at 22nm ....Intel had much advantage at all over TSMC at 20nm......certainly not in density....and the performance advantage bought then NADDA in terms of any profitable mobile design. Enlighten us.
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