Dan, The first is very low latency to local memory.
Low latency to memory is not something Intel can compete against until they start integrating the memory controller onto the CPU. (Not that Intel didn't try in the past, but that was RDRAM.)
The second is seperation of the memory and I/O busses.
I don't understand what you mean by "separation of memory and I/O busses." Are you saying Intel sticks the I/O onto the same bus as memory? LOL, that hasn't happened since the 80's.
The third is memory bandwidth that scales as sockets are added.
Irrelevant when you're talking about one specific market segment. Besides, the reverse is also true for Opteron: memory bandwidth is cut in half if you only have one out of two CPU sockets populated. (Not that it's a big deal for the 2P market, but I thought I'd toss that out there just for the sake of argument. <G>)
Intel is working to copy AMD's distributed bandwidth architecture, as it copied AMD's CPU design, but that won't be ready for a long time.
Now you're just B.S.ing as usual. Sure, Intel is going to dump the FSB eventually, but I suspect the direction Intel is going in will be "copied" by AMD once Intel gets there.
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