Replies to post #98709 on Intel Corp (INTC)

[tecate]

Hmm, sometimes we have worked in this business for years and years and years.

[wbmw]

Pentium M to Core Duo. 2x cores, same power, next generation process technology.

Pentium M "Dothan" on 90nm reached a top bin of 2.1GHz @ 21W, and was later refreshed with a bin of 2.27GHz @ 27W. There was also an LV bin of 1.6GHz @ 10W, and a ULV bin of 1.3GHz @ 5.5W.

The Core Duo "Yonah" processor on 65nm reached a top bin of 2.33GHz @ 31W, the LV bin was 1.83GHz @ 15W, and the ULV bin was 1.2GHz @ 9W.

Source: http://en.wikipedia.org/wiki/List_of_Intel_Pentium_M_microprocessors
http://en.wikipedia.org/wiki/List_of_Intel_Core_microprocessors

I would ask you to plot these power-frequency curves in Excel, draw the log based trend lines, and you will see that double the cores did not come at the same power.

They got the curves to come close by binning more SV skus at 31W (including a 1.6GHz downbin), which takes care of a lot of the low end of the leakage distribution. In other words, there were enough skus that Intel could hide the dual core impact with clever binning, but if you look at the ULV skus, it's hard for anyone to miss the fact that it took 60% more power, and there was still a loss of 1 frequency bin.

Back to Tegra 3, I don't doubt that nVidia can build a quad core A9, but they don't have a diverse set of skus like Intel does, which will limit the availability of high volume, high frequency skus, unless they increase the power budget.

At some point, these ARM designs will no longer be suitable as phone chips, and will rather be optimized for the higher power tablet form factor. Intel can add more cores and clock higher when the power budget is 3-5W, as opposed to driving down to sub-watt for smartphone form factors.

By the way, ARM's webpage shows an option for a hard macro dual core A9 on 40nm with cache and DFT features, which is performance optimized at 2GHz @ 1.9W of power. That's already substantially higher than existing phone designs. With double the cores (4 total) and all the I/O and SOC level functionality, they are going to be in the 5W of TDP range.

I do not expect the power to drop fully in half with the 28nm shrink. As I showed with your Dothan and Yonah example, it has never worked that way in the past. You can get close to a 2x power reduction with clever bin management, and selecting the very best material for the top bin, but again nVidia doesn't have the market for two dozen skus like Intel has, to put all the very best material into the top line sku.