UpNDown,
I was wondering about the improvements for K9. It seems to me that AMD is going to try to go multi-core, or at least multi-threaded with dual core. It would seem that the existing HT links might be a problem, but if it is viewed as a two level system, could not the crossbar logic be changed to allow, say, 4 to 8 cores on a chip, communicating over three HT links to 2, 4 or 8 other chips the same?
The current crossbar is designed to communicate with 2 cores (plus memory controller and HT. It does not seem like a huge conceptual change to support more cores or HT links. The crossbar will just need more ports.
As far as adding more cores, there must be diminishing returns after 2 or 4, and something else would surely become a bottleneck - a single thread performance, cache misses most often being the bottleneck of the single thread performance, so more cache or improved memory subsystem would probably be a better way to spend the silicon, rather than going beyond 4 cores.
As far as number of CPUs (chips) in the system, the sales volume drops very quickly from 2 to 4 to 8 to 16 etc.
The Tyan CEO mentioned 64 (chips or cores?). What is the current sales volume of such systems? probably barely in 1000s per year.
Adding more HT links would be really hitting diminishing returns. One possibility may be doing something similar to what Alpha did, which is to have separate I/O links and intrer-CPU links. for example, if the 4th link was added, designated to be I/O link, 3 CPU links would reduce the number of hops from 2 to 1 in a 4 way system, from 3 to 2 in an 8 way system. It would somewhat improve the current situation where from an odd situation where the ideal configuration is a 3 way (1 hop) and 7 way system (2 hop).
Joe
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