Replies to post #33594 on Advanced Micro Devices Inc (AMD)

[DARBES]

OR even none of the above.

[buck wheat]

Could be that there are some layout optimizations available at 90nm that are not possible at 130nm.

Does anyone know if layers were held constant from 130nm to 90nm? Seems like there could be a number of reasons for the "numbers not adding up.

Buck

[DDB]

"It is closer than 102mm^2 for 512k and 114mm^2 for 1 meg. It might if they can't shrink the cache transistors on the same scale as the logic ones.

Or it might be that the 114mm^2 value for the 1MB Opteron isn't valid any more. Or none of the numbers we've seen are correct."

The cache area scaled at the same rate than the core transistors (compare 130nm and 90nm die photos).

1MB L2 on 90nm Opteron = 48 mm²
512kB L2 = 24 mm²
1xHT ca. 5.2 mm²
1xMem ca. 6.4 mm²

one possible configuration:
114-24-6.4 = 83.6 mm² (Winchester? But 3xHT and 1xMem doesn't make sense, 1xHT, 2xMem is 80 mm²)
another one:
114-2*5.2 = 103.6 mm² (AMD mentioned a 102 mm² 90nm die on some conference, they could have removed unused area on the die by optimizing the layout)

For 130nm:
1xHT ca. 8.8 mm²
1xMem ca. 10.8 mm²
512kB L2 = 40.5 mm²
256kB L2 = 20.25 mm²

some cores:
193-40.5 = 152.5 mm² (Newcastle)
193-40.5-20.25-2*8.8-10.8 = 104 mm² (original 256kB Clawhammer, 1xHT, 1xMem)