Replies to post #33590 on Advanced Micro Devices Inc (AMD)

[CombJelly]

"83mm2 for 512K and 114mm2 for 1MB don't add up."

It is closer than 102mm^2 for 512k and 114mm^2 for 1 meg. It might if they can't shrink the cache transistors on the same scale as the logic ones.

Or it might be that the 114mm^2 value for the 1MB Opteron isn't valid any more. Or none of the numbers we've seen are correct.

[sgolds]

Rink, CJ, shrinks: Let's look at those numbers -

130nm 1MB Opteron: 193mm2
130nm 512K A64: 150mm2

90nm 1MB Opteron: 114mm2
90nm 512K A64: 83mm2

Implies:

512K 130nm cache = 43mm2
512K 090nm cache = 31mm2, a 28% savings

1MB 130nm cache = 86mm2
1MB 090nm cache = 62mm2 (simply doubled the 512K amounts)

130nm K8, zero cache = 107mm2 (193 - 86 = 150 - 43, check!)
090nm K8, zero cache = 052mm2 (114 - 62 = 083 - 31, check!)

So far, so good. If we assume that the core of 90nm A64 and Opteron are the same then we can conclude that 90nm A64 has the same number of HT connections and memory controllers as the 90nm Opteron.

It is curious that the cache improves only 28% while the rest of the chip improves 51%. Now we know that the roadmap shows 3 different Opteron parts at 90nm. Putting it all together:

1. A64 needs only 1 HT connection;
2. 1XX Opteron needs only 1 HT connection;
3. 1XX 130nm Opteron has 3 HT connections, 2 silent;
4. 90nm zero cache size improved more than a shrink would predict;
5. At 90nm (sockets 940, 939) both Opteron and A64 use 2 memory controllers.

This leads me to conclude that the Opteron used for this example only has 1 HT (1XX model only) and the extra space savings came from dropping the two unused HTs.