The greater physical thickness of the most critical structure on the chip means less manufacturing variation with hik/mg, not more
I think it's an alignment thing, not a thickness thing. Intel described going to "gate last" rather than "gate first" and this has raised speculation about gate alignment and TPTs. Here is a private mail message from a non-Intel process guy. I'll withhold his name:
the gate first stuff was done because of self alignment. I just can't see them holding a .5 nm tolerance on the gate last stuff. Seems like it is well beyond both mask and stepper technology. this is the cause of non overlap on gates and increases the leakage on the sides of the gate.
I can see them having the yeild high but not at high volumes (read fast thruput).
But then most of these process engineers surprise the heck out of me all the time.
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