Going into 45nm currently only offers performance-advantages if you use technologies like MG/Hi-K stacks - which come at a price: It significantly increases variation.
This is nonsense. The high K property of the gate dielectric allows its physical thickness to be greater than the ~1.2 nm that nitrided SiO2 is limited to while having better control of channel inversion and conduction. The greater physical thickness of the most critical structure on the chip means less manufacturing variation with hik/mg, not more.
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