Replies to post #48714 on Intel Corp (INTC)

[ChipGeek]

It is not clear if the 4 core chip has 1 or 2 CSI channels[20 bit wide]. I think that the chip has two independent memory paths,one on the right and one on the left.

Performance Scalability: Eight core chip will be obtained by mirroring the chip vertically and doubling the CSI and memory channels.Two core chip will be obtained by cutting it in half, with half the memory buffers, and half the CSI resources. Obviously the control logic in the central vertical path cannot be neatly sliced, and most of it will be retained. So external memory and interconnect bandwidth scale with the number of cores. So performance scales linearly with number of cores.

Nice analysis. Very nice indeed...

[wbmw]

Nehalem Die Size:

Here's a good image of a Nehalem wafer:



I count about 22x16 die on a 300mm wafer.

That makes the die dimensions about 13.6mm x 18.8mm.

I'll make a gross estimate of 255mm^2. Heh, smaller than Barcelona, and I bet it has a heck of a lot more L3 cache. <G>