Replies to post #48718 on Intel Corp (INTC)

[Saturn V]

Hi ChipGeek,
Hans DeVries has gotten hold of a high resolution photograph of Nehalem and has performed his analysis on ACE:
http://aceshardware.freeforums.org/viewtopic.php?t=141

I think that he may made some errors:
A. He shows the L2 interspersed within a shared L3. Seems tricky.
B. He shows a 3 channel memory interface. For a scaling to 2 core product, I would have expected either a 2 or 4 channel interface.

Are you in a position to comment ?