Keep staring at that die...
Nehalem speculations in lieu of HansDeVries:
It is not clear if the 4 core chip has 1 or 2 CSI channels[20 bit wide]. I think that the chip has two independent memory paths,one on the right and one on the left.
Performance Scalability: Eight core chip will be obtained by mirroring the chip vertically and doubling the CSI and memory channels.Two core chip will be obtained by cutting it in half, with half the memory buffers, and half the CSI resources. Obviously the control logic in the central vertical path cannot be neatly sliced, and most of it will be retained. So external memory and interconnect bandwidth scale with the number of cores. So performance scales linearly with number of cores.
Power Scalability follows by each core having its independent clock, which can be shut off independently,as in Barcelona.However if a thread is shut off, the power savings are small since the L1/L2/ALU still need to be powered, but half the register file can be shut off.
Unknowns: Die Size ? Power per core ? Performance ?
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