I’m sorry Ted, I really do enjoy reading most of what you post, and as with everything, I try to do my own DD and take things with a grain of salt. But this post is extremely hypocritical of you. Maybe consider taking a few days off from posting. Let things cool down. Perfect time of the year for it as well.
teddybear said, let's agree not to sabatoge our investment.
OUR investment?? 🤣🤣🤣
Ok, I'm really trying to keep a straight face here but come on ted "OUR investment"?
Ok, I'll play along then and let's see how LONG this lasts, and for now my new nickname for you will be teddyturner since you now have "tuned" to become a Long the likes of Walter, Jeunke, X, and myself, but I'm going to have to keep you on double secret probation until further notice just to be sure this isn't somehow another elaborate rouse
the chances of LWLG's Perk "going wrong" in any Fortune Global 500 Device builds are slim to none, the LWLG Perk materials are protected by an ALD encapsulation barrier that in its Gen2 passed Telcordia's most stringent 85/85 test with flying colors, that ALD encapsulation is now at Gen4 and is off the charts incredible barrier measured to be 500% stronger barrier than what has been the Industry Standard used for the past 20 or 30 years, that being the "gold box", so that barrier exists whether just testing the materials or any device the material is put into, and you can shake it and bake it and do whatever you want to it put it will not hurt it, so if the completed Transceiver powered by LWLG fails it won't be because of LWLG's modulator, see Slide 13 to understand better why LWLG will be the ONLY choice for true next-gen internet transmissions and ALL the giant companies will need to adopt it or perish!!
Plus >>>> Slide 22 BEOL Process SAME for all Foundries!! Nice!!
• The backend PDK is developed for applying EO polymers on the modulator device fabricated by a standard silicon photonics process (not foundry-specific) • Key PDK steps • EO Polymer Deposition • EO Polymer Patterning and Etching • Encapsulation • Contact Pad Opening • Wafer Level Poling and Test • The manufacturing process is compatible with semiconductor fabrication lines using standard high-volume tools
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