Here is a response below All to your worry per B and C another highly knowledgeable poster with a keen understanding of Poets products( from Agoracom this morning)
“The danger of a faulty understanding is that it leads to decision making based on a falsehood.
There is no physics-defying fitting of a larger object into a smaller one. A packaged light source (data) is external to an ASIC chip and the data travels by fiber optical cable which connects to the ASIC chip by a FAU (Fiber Attach Unit). “
Allwillbe said, Here’s the big issue I have in that time frame.
That’s the planned ramp up for Celestial AI photonic fabric. That Photonic Fabric is being co designed with Broadcom using TSMC’s 5 nm Chip on wafer on substrate technology that will utilize TSMc’s Compact Universal Photonic Engine(COUPE).
The Photonic Fabric has to utilize the smallest node available because of the neuromorphic computing capabilities required to create the massive scale of chip to chip and within chip data processing.
Poet’s optical engines are measured in millimeters vs nanometers by TSMC.
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