How much extra space is required to add multiple ports to the cache (ie maybe have 4-8 read ports available to the L2 cache, so that it may be shared among all the processors on the single die - one wouldn't need to have as many ports as the number of processors, as some CPUs would be accessing L1, and some not req memory access at that time at all). If it is possible, it should help power dissipation as well as the extra leakage from duplicating all the cache would no longer be a problem.
True multi-ported (at the memory cell level) cache grows
rapidly in size and access latency with the number of ports.
Memory tends to be metal limited and each port adds a word
line running in one direction and a couple of bit lines in
the other direction. There are different ways to implement
even basic cache so it is hard to come up with single hard
number but even going to two ports more than doubles the
area of the SRAM cell. The affect in performance will be
bad for typical sizes of L2s.
Historically uP designers go out of their way to avoid true
cell level multiported caches. The Alpha EV5 dcache is dual
ported by having duplicated arrays. The Alpha EV6 dcache
is dual ported by double pumping the arrays every processor
clock cycle. The K7 dcache is pseudo dual ported - its 64KB
is divided into eight 8 KB banks. Two accesses in a cycle
only occurs if the accesses are to different banks. The I2
L2 cache is also pseudo multiported. True cell level multi-
ported caches tend to be small and first level only, and are
rather power hungry.
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