How much extra space is required to add multiple ports to the cache (ie maybe have 4-8 read ports available to the L2 cache, so that it may be shared among all the processors on the single die - one wouldn't need to have as many ports as the number of processors, as some CPUs would be accessing L1, and some not req memory access at that time at all). If it is possible, it should help power dissipation as well as the extra leakage from duplicating all the cache would no longer be a problem.
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