Replies to post #4887 on AMD strictly moderated (AMD)

[chipdesigner]

That seals it. It is helpful to go back to some of wbmw's original errant claims, like this one:

http://www.investorshub.com/boards/read_msg.asp?message_id=11034627

The IMC is a wonderful contributer to performance on the K8, but it's not the primary one.

Bzzzt.

[wbmw]

Re: Only a persistent obstinate fool would contend otherwise with these actual 20% figures being quoted.

You've described yourself exactly, since you are the one looking at "up to 20%" and obstinately and persistently claiming it is an "actual 20%" figure. The only difference is that you are finding multiple links that repeat the same quote, but you can find a million, and it still doesn't change the fact that it's based on a quote that puts 20% on the optimistic side of expectations.

As Chipguy said, pointer rich code misses cache a lot and relies on memory. And sparse transfers will lose the benefit of pipelining, so first-to-load latency becomes a first-order performance limiter. But even in those cases, you don't miss cache 100% of the time, so those 50% savings in first-to-load latency don't ever gain 50% in performance. According to AMD, up to 20% is possible, but you will most likely see less than this in most apps.

Get over it. You lost this one, Mas.