Replies to post #132156 on Intel Corp (INTC)

[Redwood1205]

You are exactly in point.
Intel is like an aircraft carrier. They decided to focus on lower power and they probably designed to low. Their competitors have boosted cores and clocks(raising power to the max) in order to remain competitive on performance with Intel.
Intel now has a lot of room to increase performance relative to competitors.
Many make a big point of single core performance of the A7 but doesn't the wide core A7's take advantage of parallelism in the code. How is this different then two cores. If Amdahl's Law applies, additional cores may not speed up apps with a lot of serialism.

[alexander-dumbass]

Geekbench3 86% 32kb L1 Reads hit and 94% Writes hit. I downloaded and ran the standard PINTOOL dcache tool and ran on my Linux i7-4700.

The AES "integer benchmark" on my i7-4700, is executed with the AESENC instruction which comprises 0.06% of the instructions but is given 10% to 15% weight in the "integer" metric.

The A7 includes has added not only the AES instructions but all the SHA instructions. They not only break the AES benchmark but also the SHA benchmarks. Breaking two benchmarks with new instructions impacts 25% of the "integer" metric portion.

It looks like the A7 is the first Apple design that uses a 64-bit bus to memory. That is likely the source of most of the performance increase AND the power consumption bump. That is when the process and leakage and .... gain importance.

Disclaimer: I think Geekbench is unrepresentative of anything.


PIN:MEMLATENCIES 1.0. 0x0
#
# DCACHE stats
#
# L1 Data Cache:
# Load-Hits: 218373856747 86.17%
# Load-Misses: 35057173434 13.83%
# Load-Accesses: 253431030181 100.00%
#
# Store-Hits: 86846876370 94.45%
# Store-Misses: 5102192868 5.55%
# Store-Accesses: 91949069238 100.00%
#
# Total-Hits: 305220733117 88.37%
# Total-Misses: 40159366302 11.63%
# Total-Accesses: 345380099419 100.00%


Processor Name: Intel(R) Core(TM) i7-4770 CPU @ 3.40GHz
L1 Instruction Cache: 4 x 32 KB
L1 Data Cache: 4 x 32 KB
L2 Cache: 4 x 256 KB
L3 Cache: 8 MB

[mas]

Nevertheless, Intel needs to speed up its Core line significantly. They were too concentrated on bringing power down, which was important, but performance needs to increase more than 10% per generation.

It's a question of priorities. Basically from 65nm Core 2 to 14nm Broadwell Intel has increased performance/clock by a factor of 2-3 while reducing power by a factor of 4-5. It would not have been possible to reduce power by a greater factor than performance increased if the performance increase had not been limited by maintaining a constant quad-issue pipeline all through those generations.

This limited the performance gain but will eventually allow the Broadwell-Y to play in the same fanless sockets as traditional ARM chips which is quite an achievement for a traditional high-performance PC processor. The turbo ones will be able to maintain the traditional Intel high performance advantage but in a new fanless environment thereby increasing the TAM for expensive Intel high performance chips. I suspect having reached this important market positioning benchmark Skylake will change the development priority and concentrate more on performance going forward especially as Atom is supporting it well now in mobile performance.