Zeev's Turnips Patch-No Politics (ZEEV)

[goodluck]

Hey, Zeev, is Eitan another Ovshinsky? Or is he the "real deal"? Any opinions? You can wait till after the close, if time is short now.

Memories look to new materials set

David Lammers
Dec 19, 2005 (10:00 AM)
URL: http://www.commsdesign.com/showArticle.jhtml?articleID=175006444

Austin, Texas — Over the last five years, changes to logic devices have grabbed much of the industry's attention, as copper, low-k dielectrics and strained silicon were introduced to keep scaling on track. Now, memories are set to undergo an equally dramatic series of materials and design changes, ranging from new dielectrics in DRAM and flash to SRAMs with eight transistors per cell, said participants at the recent International Electron Devices Meeting in Washington.


The chip industry overall achieved about 7 percent growth this year, largely due to strong sales of NAND flash memories. NAND cells are small and inexpensive to make, and companies making DRAMs can easily adapt their DRAM manufacturing processes to NAND. But as NAND cells become smaller, they tend to interfere with their neighboring cells. Also, reliability is a major challenge: The floating gate will soon have only about 1,000 electrons to store each bit, declining to only about 100 electrons at the 30-nanometer node. At IEDM, participants at an evening panel on nonvolatile memory scaling were in rough agreement that floating-gate flash will need to be overhauled at the 32-nm node, coming in at the end of this decade.


Albert Fazio, director of flash memory technology development at Intel Corp., said that flash must undergo "real structural change," probably at the 22-nm node. "Few people in the industry realize that compared with logic, flash uses an order-of-magnitude fewer electrons for data retention," he said.


"Adjacent-cell interference will require a high-k interpoly dielectric as we make the floating gate thinner," said Toshitake Yaegashi, a NAND engineering manager at Toshiba Corp. "At Toshiba, we believe the reliability issue is not as severe as the adjacent-cell coupling issue."


During the nonvolatile-memory sessions at IEDM, Kinam Kim, memory development manager at Samsung Electronics Co. Ltd., described a new dielectric and gate electrode structure, called Tanos, which Samsung has demonstrated in a 4-Gbit NAND cell. The dielectric combines silicon dioxide with nitrogen and aluminum oxide, and works with a gate electrode made of tantalum nitride.

Faster erase times
The Tanos test chip moves to a "Sonos-like" approach of trapping charge in a nitride layer sandwiched between silicon and oxygen. Kim said the high-k dielectric's bandgap characteristics match up well with the charge-trapping layer. The result is an improved coupling ratio on the tunnel oxide. The thicker dielectric used in the Tanos approach will provide for faster erase times, while cutting the charge loss, Kim said.


While the 4-Gbit test chip used 60-nm design rules, the approach will scale going to the 20-nm node and perhaps beyond, Kim said.


Jungdal Choi, a Samsung flash process technology manager, said Samsung has developed a U-shaped storage capacitor and tested it at 50-nm design rules. At the 35-nm node, Samsung believes it will take a number of innovations to continue to scale NAND flash, ranging from the Tanos approach to a Sonos-type bit cell, multibit-per-cell technology, cell stacking, higher-k dielectrics and even "double photo patterning," in which the lithographic steps are repeated in an offset-exposure technique to achieve tighter design rules.


If Samsung moves to a Sonos-type structure, will Toshiba and others also move away from a floating-gate approach?

Yaegashi said Toshiba believes it is difficult to achieve a multilevel-cell architecture with a Sonos-type memory. Toshiba has other ideas, including a 3-D cell structure and new dielectric materials. By optimizing the threshold-voltage distribution and reducing process-induced stress damage on the floating gate, Toshiba may continue to scale the floating-gate approach, he said.


Toshiba, its partner SanDisk, and Intel and Spansion in the NOR-flash market are among the companies that have embraced multilevel-cell technology as a means of cost-effectively doubling chip density. Samsung has adopted MLC technology only for its highest-density NAND parts, aimed at music and video storage, where a dropped bit has little consequence.

Saifun Semiconductors Ltd. (Netanya, Israel) described a 4-bit-per-cell nonvolatile-memory architecture, paying particular attention to reliability. Saifun has licensed its approach to seven companies thus far, including Macronix, Fujitsu and Spansion, the flash spin-off from AMD.

"Clearly, it is impossible to scale floating-gate flash properly because of coupling from one floating gate to the neighboring floating gate," said Saifun CEO Boaz Eitan. "We believe the oomph in the industry will come from storing bits in ONO structures, which have much better simplicity."

The Saifun approach used today stores 2 bits per cell, trapping electrons in each corner of the nitride layer. To get to 4 bits/cell, Saifun uses four levels of threshold voltage to create 2 bits in each corner of the bit cell. The programming algorithm can be altered as needed to move from 2 bits/cell to 4, depending on the application. For floating-gate flash, achieving 4 bits/cell would require 16 threshold-voltage levels.

Eitan said that Saifun's approach supports 3 Mbytes/second of write performance. As the company's licensees prepare 8- and 16-Gbit flash chips using the 4-bits/cell approach, Saifun's R&D team is working on 8 bits per cell. "I am very certain that 4 [bits/cell] is not the end of the road," Eitan said.


Critics argue that Saifun's approach is more difficult to manufacture than conventional NAND flash, and that the hot-electron and hot-hole injection techniques used to program and erase may require more power than floating-gate flash.


Saifun's demonstration of 4 bits/cell for a nitride storage-type flash raised questions about whether emerging memory types, such as phase-change and magnetoresistive (MRAM) products, will be able to compete on costs with the nitride-storage nonvolatile memories.


Freescale Semiconductor Inc. presented an MRAM that uses magnesium oxide, rather than an aluminum material, in the write layer. Saied Tehrani, director of MRAM technology, said Freescale will replace aluminum oxide with magnesium oxide, which will improve the bit resistance during the write cycle. Also, the tunneling layer can be thinned slightly.


Sony Corp. went to IEDM with a spin-type MRAM, which also sharply reduces the MRAM write current — the Achilles' heel of the MRAM approach thus far (see story, page 26). Spin RAM takes advantage of the spin torque of electrons to achieve a 2-nanosecond switching speed at about 300 microamperes of power — about 5 percent of the power needed to switch a conventional MRAM cell.