It seems the lower IPC/higher frequency route leads to more power usage -- more logic gates driven at a higher speed. Please explain where I'm wrong?
To go down the path of higher IPC your processor needs
to be able to issue and execute more instructions in
parallel, i.e. wider issue.
Going wider means geometrically more complicated decode,
control, and datapath bypass logic (the triple way parallel
x86 decoder in K7/K8 is probably at least an order of
magnitude more complex than the single decoder in P4).
It also means that more signals have to travel around
the chip farther and that implies more wires, longer
wires, and far more repeaters. Going wider also has its
own inefficiencies. If the parallelism isn't present in
the code then that complicated logic runs for the sake
of finding reasons to keep execution units idle.
The power scaling differs in minor ways from going the
speed racer route vs the brainiac approach which is why
I said the power wouldn't vary greatly for a given level
of performance, not that it wouldn't vary. Also, the
growing issue of device leakage changes the picture
somewhat. Leakage isn't very sensitive to clock rate
but it is to transistor count. That would normally tend
to favor the speed racer but Intel is adding complexity
to its x86 cores at a far too high a rate to benefit
from this effect.
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