chipguy, on logic gates and speed
Regardless of whether a given level
of performance is obtained by wiggling many logic gates
relatively slowly or fewer gates faster, the amount of
power consumed won't vary greatly for a given process
feature size and supply voltage.
But wouldn't a longer pipeline imply more need for temporary storage, rename registers, etc.? Thus, a longer pipeline would need more logic gates, but with smaller per-cycle work units, allow higher frequencies? The higher frequencies would allow the undesirable effects of the longer pipeline on branch mispredictions or other fault to be compensated for (and more so) by higher frequency?
It seems the lower IPC/higher frequency route leads to more power usage -- more logic gates driven at a higher speed. Please explain where I'm wrong?
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