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Wednesday, June 26, 2019 9:07:21 AM
Moore’s Law Now Requires Advanced Packaging
Experts at the Table, part 1: Shrinking features isn’t enough anymore. The big challenge now is how to achieve economies of scale and minimize complex integration issues.
APRIL 18TH, 2019 - BY: ED SPERLING
https://semiengineering.com/moores-law-now-requires-advanced-packaging/
Excerpt > Silicon interposers are now causing trouble with electrical loss and power noise and signal integrity. Corning’s CTO recently talked about glass interposers. The glass interposer has the highest resistivity and very low loss. Some of our end customers and the foundries are now talking about that in order to enable 5G, ADAS, AI, HBM2, and chiplets. That’s becoming the new paradigm of meeting extremely low latency rates and high performance.
Based on LWLG's patents it seems that LWLG would be using it's own Polymer Interposer, but perhaps in the shorter-term would use another maker's Interposer, from what I have seen, all Interposer's do wafer level hermaetic sealing
Experts at the Table, part 1: Shrinking features isn’t enough anymore. The big challenge now is how to achieve economies of scale and minimize complex integration issues.
APRIL 18TH, 2019 - BY: ED SPERLING
https://semiengineering.com/moores-law-now-requires-advanced-packaging/
Excerpt > Silicon interposers are now causing trouble with electrical loss and power noise and signal integrity. Corning’s CTO recently talked about glass interposers. The glass interposer has the highest resistivity and very low loss. Some of our end customers and the foundries are now talking about that in order to enable 5G, ADAS, AI, HBM2, and chiplets. That’s becoming the new paradigm of meeting extremely low latency rates and high performance.
Based on LWLG's patents it seems that LWLG would be using it's own Polymer Interposer, but perhaps in the shorter-term would use another maker's Interposer, from what I have seen, all Interposer's do wafer level hermaetic sealing
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