Lightwave Logic Inc (LWLG)

[prototype_101]

THE FUTURE (Ayars - Rut-Roh)

Despite the tantalizing possibilities for the future of the technology, there is a limit to what is physically possible. Rockley Photonics CEO Andrew Rickman’s view is that the future of optical connectivity is in-package optics, with optimized silicon photonics and microelectronics dice in the same package rather than on the same die.

“The behavior of photons and electrons is vastly different,” said Rickman. “As a result, the process that is needed to develop the most optimized electrical ICs will be different from the process needed to develop the most optimized photonics ICs. This is why monolithic integration — while it is a seductive idea — can never realize the full potential of silicon photonics. We now have significant innovation in packaging technology, such as 2.5D and 3D wafer-level packaging, that can be used to develop and manufacture the most effective overall solution, and we see this approach lasting for some time.”

Rickman noted that lasers need to be implemented in direct-bandgap (III–V) materials, so all silicon photonics solutions will need multiple dice anyway. Instead of further integration, correct partitioning of the solution onto different dice is key, he said.

“We believe that, ultimately, the optimal solution will monolithically integrate the digital content and the analog front end, while the silicon photonics and lasers remain in separate processes — this is the approach we demonstrated with Topanga,” Rickman said, referring to the company’s demonstrator device from OFC ’18.

Rockley Photonics’ in-package optics platform allows the transceivers (purple) to be mounted close to the ASIC (gray). (Image: Rockley Photonics)
Topanga is a 12-port 100G Ethernet switch with all 12 100G transceivers pre-installed. It uses an in-house–designed 1.2-Tb/s Ethernet switch ASIC with Layer 3 routing capability, plus the analog front ends (AFEs) for all 48× 25-Gb/s electrical channels. The ASIC is co-packaged with silicon photonic ICs implementing optical interfaces based on parallel single-mode fiber. The optical power is provided by external laser modules. The PICs are mounted directly adjacent to the CMOS die to minimize the length of the high-speed electrical channels, simplifying their design and reducing power consumption.

Until such time as Rockley’s vision of in-package optics becomes widespread, Rickman said, a likely intermediate solution would use separate dice for the AFE and silicon photonic PICs, assembled into the same package, with a standard electrical interface for interoperability with a third-party switch chip. Rockley is pursuing this approach with its LightDriver offering, a switch-agnostic platform for multiple segments, including data center connectivity, consumer sensors, and LiDAR. The company demonstrated a transmit-receive optical subassembly using this platform at OFC ’19. Future systems built on the platform may be further optimized at the system level, perhaps with denser integration with the digital ASIC or via optimized electrical interconnects, Rickman said.

Rickman also argued that despite any hype to the contrary, silicon photonics is not compatible with advanced CMOS nodes, because of the properties of light. “Most companies building silicon photonics chipsets come from a microelectronics legacy based on an old but still unproven strategy to leverage existing silicon CMOS foundries and processes,” he said. “The problem is that photons and electrons have vastly different behaviors and, therefore, CMOS nodes optimized for electrons are not necessarily the best choice for highly optimized photonics circuits.”

There are several resulting practical considerations. Silicon photonics requires an SOI CMOS process, which is not available at the same advanced nodes as standard CMOS, and certain processing steps are required that are not available in the standard process flow. Also, for a high-speed modulator to work in silicon, the waveguide must shrink to submicron sizes, much smaller than the wavelength of the light passing through it. At these tiny geometries, the propagation losses increase and efficiency decreases.

“It’s important to keep in mind that photonic devices are large compared to transistors,” said Rickman. “Using up extremely valuable area on a 7-nm die to implement photonic circuits leaves less room for the chip’s high-speed digital content. We believe that this is not an economically viable approach. While the Rockley platform is fully capable of producing all the functional elements that are possible in a standard CMOS-derived process flow, a benefit of our platform is that it also has all the elements, design features, and material systems available for photonic-optimized solutions.”

https://www.eetimes.eu/2019/04/26/silicon-photonics-reaches-prime-time/

Ok, so bottom line, a monolithic SiP chip is likely not a solution based on Andrew Rickman's comments here, but the co-packaging of optics/electronics is a worable solution as Dr Lebby was speaking to at the ASM at 1:01:01

ASM Q&A at about 1:01:01 Dr Lebby talks about how LWLG's technology is perfectly positioned for the Photonics Industry's rapid trend towards CO-PACKAGING

Dr Lebby said "we (LWLG) are actually ideally positioned for this new trend that's just occurring where other technologies are going to suffer"

https://investorshub.advfn.com/boards/read_msg.aspx?message_id=148895377

excerpts from Ayars recent paper (Rut-Roh),

. For example, it has been challenging for this technology to achieve 25 Gb/s modulation even into relatively small photonic loads such as ring-based optical modulators

. However, a major challenge in monolithic integration is that process optimizations for photonics and electronics cannot be performed independently of each other. As such, the transistors in monolithic platforms tend to derive from older CMOS processes, where transistor properties are not so sensitive to fabrication changes for photonics

Due to the limited transistor speed scaling in advanced processes, and relative increase in transistor and interconnect parasitics, link speeds in excess of 50 Gsymbol/s will be highly energy inefficient, while links above 100 Gsymbol/s will be very difficult to realize. Utilizing the microring-based DWDM technology with large bandwidth density allows for line rates per wavelength to stay in the energy-efficient regime of around 25 Gsymbol/s, while growing the overall system throughput by adding more wavelengths

(Rockley was one of the finalists for the Best PIC Achievement award won by LWLG, oh, and did I mention that Intel was also one of the finalists LWLG's technology won out over! ...but Ayars? not so much...)