Rim Semiconductor Company (fka RSMI)

[McCloud]

If I followed all this, I would have to assume that when Brad spoke of using someone elses chip and adding our code to it, he would have been speaking of a structured ASIC chip. Then the use of a structured ASIC seams to be a low volume stop gap between FPGA and ASIC. FPGA may be too bulky to use and therefore we would need something that would fit until the full ASIC could be produced. From what RET EE said about costs, it would seam a high price to pay for an intermediate step. This could be necessary if deployment of the Triple PLay within a time frame were necessary regardless of cost to some customer.

However, I may have some cofusion between the statement that an ASIC takes 6 months to produce and I believe it was Moxon who stated that he had produced 135 ASICs in one year. I know he personally didn't produce them and there was a large staff, however, if they take 6 months doing 135 of them seams difficult to do in a year. That makes me suspicious of the 6 months figure.

Ernie