Intel Corp (INTC)

[themYokes]

Real world matters, not a hypothetic SRAM cell.

Haha you are unbelieveable. You do realise that the L2 and L3 cache you quote are entirely SRAM. And the figures I quoted are from GloFlo and Intel published papers.

There is no confusion. Intel has the denser 14nm of ANY foundry process by ANY measure.

How Intel's CPU architects use this process to implement their logic and what tradeoffs they are making for Clock speed, reliability etc. is entirely their choice. But do not confuse process with design.

Dont insult my intelligence by quoting me Zepplin die figures provided by AMD in a PROCESS discussion we are having with regards to GloFlo