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I looked in my closet, and there was Donovan.
remove the ]
yes, for a while they overscaled gate length, then slowed down.
Intel process => gate length
65nm => 35nm
45nm => 35nm
32nm => 30nm
22nm => 25nm
14nm => 20nm
Performance Enhancement for 14nm High Volume Manufacturing Microprocessor and System on a Chip Processes
https://www.researchgate.net/publication/303896155_Performance_Enhancement_for_14nm_High_Volume_Manufacturing_Microprocessor_and_System_on_a_Chip_Processes
Interesting paper on backend improvements for 14nm.
Re: Xeon E5 v4
Die | process | area | transistor count
------------|---------|---------|-----------------
SNB 8 Core | 32nm | 435 mm2 | 2.7 billion
HSW 12 Core | 22nm | 492 mm2 | 3.8 billion
BDW 24 Core | 14nm | 456 mm2 | 7.2 billion
I'm listening to tech insight by Alan Gara.
Unfortunately Intel has decided to replace him with rapper 50 cent by the end of the year ;) (just kidding)
Following the delay of Skylake processors, Intel's next-generation Kaby Lake
Skylake has not been delayed.
ex falso quodlibet.
Renée has contributed immeasurably to Intel
-BK
haha, too small to measure.
this reminded me how Glenn Hinton explained that 2-way SMT is the sweet spot:
"if it's not you, it's me!"
cooperation between two threads is easier. just like with people.
they'll take them to the pawn shop.
maybe trojan horse Anand C. designed the chip.
I haven't made any mistakes in my post. I just quoted some specs from ark.intel.com. You've heart my feelings, you should apologize.
IVB-Y vs. HSW-Y vs. BDW-Y
http://ark.intel.com/compare/72015,76618,83612
IVB-Y HSW-Y BDW-Y
Launch Date Q1'13 Q3'13 Q3'14
CPU Mhz Base 1500 1700 1100
GPU MHz Base 350 200 100
Tjunction C 105 100 95
Max TDP W 13 11.5 4.5
Broadwell Geekbench 3 score
FWIW
Intel Corporation Broadwell Client platform
http://browser.primatelabs.com/geekbench3/compare/209579?baseline=679327
Maybe you were thinking of ferromagnetics?
Of course ;) I'm not an EE, just lowly computer science.
And armchair Intel senior fellow in my spare time.
can't be fun being a salesman for the competitors.
if only WiMax had won the battle...
good point, maybe in the future it will be integrated on the PCH that uses a more analog friendly process tech.
Actually I think the following partition may make sense for future products:
- main die optimized for logic, containing cores, graphics cores and SRAM cache. (using III-V tunnel transistors or GeSn gate-all-around CMOS). extremely low voltage allows very-low k interconnect. More thick metal layers will be used to allow transmission line interconnect between the cores, solving the RC scaling problem.
- PCH die optimized for analog and eDRAM. PCH will include all IO, even memory IO (!) and a huge eDRAM cache. The eDRAM will ensure that PCH die size is not bump limited.
- main die and PCH die linked by very low power IO (MCP, 2.5D interposer, TSV ?)
---------------
FIVR uses air core inductors, so it's not really magnetics.
My guess is that the high switching frequency (140 MHZ) also helps a lot to reduce the influence of the inductors/capacitors.
Intel has researched CMOS backend magnetic material layers above the metal layers, but now I assume this will not come anytime soon.
Intel claims that HSW FIVR is economically feasible because FIVR can be spread across the main die, using bumps borrowed from neighbouring regions that do not need them.
HSW FIVR has VCCIN at 1.8V. HSW FIVR uses thin-gate transitors in a cascode configuration that allows operation at 2xVMAX.
So for Broadwell I expect higher switching frequencies because of better transistors. (~170 Mhz ?). This will reduce the physical size of the ACIs and also the inductive losses.
VCCIN may drop to 1.6V, but this is ok as the operating voltage is lower as well. If Intel will offer thick gate transistors on their standard CPU process at 14nm, VCCIN could stay at 1.8V. (but maybe backend dielectric reliability is the real problem...)
IDC team is magic or something, and the Oregon team is utter crap.
Well, SandyBridge really improved upon Nehalem.
So there is hope.
Maybe Skylake will have lots of small VRs for each functional block inside of a core.
I don't like that the design teams seem to play a little bit of ping-pong:
- Prescott: HyperThreading
- Merom: No HyperThreading
- Nehalem: HyperThreading back, LLC on own voltage rail.
- SandyBridge: LLC on core voltage rail.
- Haswell: LLC on own voltage rail.
BTW, Skylake Y-Line-B still seems to have FIVR according to the leaked slides.
And that site deepdyve is really great!
Haswell FIVR paper
https://www.deepdyve.com/lp/institute-of-electrical-and-electronics-engineers/fivr-fully-integrated-voltage-regulators-on-4th-generation-intel-core-W88eUoKR43
You can get a 5 minute preview for free.
I'm sad to see FIVR go away.
Anyway, Skylake may still have some kind of IVRs on the die, just a less broad implementation (i.e using IVRs only for quick voltages changes for each core and to ultra low voltages).
Also, FIVR uses buck convertes with package inductors. They may have decided that buck convertes with thick metal inductors, linear regulators or switching-cap converters are better suited for this task.
See this VLSI 2014 paper:
A 500 MHz, 68% Efficient, Fully On Die Digitally Controlled Buck Voltage Regulator on 22nm Tri-Gate CMOS
Morganfield
there will be a version of it with Itanium cores for ultra-RAS phones. The codename is "McKinley Morganfield".
The SOC is called "Muddy Waters".
just a wild guess on my part.
is Jen-Hsun Huang preparing another lawsuit ?
They killed Tegra i with their contra-revenue
whopping 3x relative to 22nm
Broadwell has a lot of IO circuits that do not scale 2x or 3x.
peanuts.. you have to look at the big picture
Intel Chronicles #3
January 2001:
Intel CEO Craig Barrett unveals the Intel Web Tablet (codenamed "IPAD") featurig touch control. It is later canceled.
January 2007:
Steve Jobs unveals the Apple iPhone.
August 2009:
Intel details the "Moorestown" platform for smartphones at the Hot Chips conference.
It is based on a 45nm SOC process featuring revolutionary hafnium-based high-k metal gate transistors.
January 2010:
Steve Jobs unveals the Apple iPad.
February 2014:
Intel launches the "Merrifield" platform for smartphones.
It is based on a 22nm SOC process featuring revolutionary tri-gate transistors.
Intel Chronicles #2
July 18, 2006:
Intel launches the Montecito processor.
Montecito is a dual core Itanium server processor featuring 24 MB L3 cache and 1.7 billion transistors.
(90nm)
Feb 18, 2014:
Intel launches the Ivytown processor.
Ivytown is a multi-core Xeon server processor featuring 37.5 MB L3 cache and 4.3 billion transitors.
(22nm)
Intel Chronicles #1
January 15, 2008:
Steve Jobs unveils MacBook Air, weighing 1.36 kg.
It features a 1.6 ghz Intel dual core processor with 4 MB cache. (65nm).
April 29, 2014:
Apple releases 7th update of MacBook Air, weighing 1.34 kg.
It features a 1.4 ghz Intel dual core processor with 3 MB cache. (22nm).
Intel 14nm presentation at Global Leadership Summit
http://www.intc.com/common/download/download.cfm?companyid=INTC&fileid=739925&filekey=ADC805CA-834D-4A22-BBFB-0A56E5E4534E&filename=GLS_Bohr_2014.pdf
Intel at 2014 VLSI Symposium Circuits
most interesting:
- A 2GHz-to-7.5GHz Quadrature Clock Generator Using Digital Delay Locked Loops for Multi-Standard I/Os in 14nm CMOS.
- 2nd Generation Embedded DRAM with 4X Lower Self Refresh Power in 22nm Tri-Gate CMOS Technology.
http://www.vlsisymposium.org/wp-content/uploads/2013/06/Circ-14-program.pdf
Intel Custom Foundry Demonstrates Industry-Leading General Purpose SerDes on 14nm Process
SOI wafer sales down
DX4 already had 16KB L1 cache.
We will see. 14nm should be dense enough to support an economic 2C+GT3+EDRAM. But you are right, maybe it is the time of die stacking with TSV.
Or maybe just eDRAM for the frame buffer, as AnandTech has speculated.
But I question AnandTech reasoning on 14nm. Maybe CrystalWell ported to 14nm will actually be the first shipping 14nm die. it seems to be one big cache, so the yields should be pretty good.
But it's all pretty clear that Intel will have the option to obsolete nvidia at 14nm. new microarticture (gen8) + lots of edram/packaging options.
Haswell is quite an engineering feat.
transistors,microarchitecture,packaging,FIVR,eDRAM etc.
I want to upgrade to an Haswell ultrabook.
My speculation about future products:
- server Haswell-EX with big eDRAM cache ?
- Broadwell integrating eDRAM on same die for ultrabooks ?
It seems a lot notebook manufactures continue to use extra nvidia chips, though.
I think this is more of a political/marketing thing.
re Kittson at 22nm
I think the Hot Chips 2011 presenter for Poulson stated that porting to "future process generations" was his "day job". So the change of plan must have come pretty late.
Alpha-particle Induced Soft Error Rates in 22nm Bulk Tri-Gate Technologies.
https://sites.google.com/site/ieeescvserworkshop/Presentations
"Two complete Ultrabook Vcore solutions by IR save space and battery life"