Intel Corp (INTC)

[jokerman]

Alpha-particle Induced Soft Error Rates in 22nm Bulk Tri-Gate Technologies.

https://sites.google.com/site/ieeescvserworkshop/Presentations

In this paper, we present the measured alpha-particle soft error rate (SER) of latches and flip-flops implemented in 22nm high-k + metal gate bulk Tri-Gate technology. While the high energy neutron SER in 22nm Tri-Gate devices can be up to 4x lower compared to its 32nm planar counterparts, the observed alpha-particle induced SER reduction is in excess of 10x. This benefit can be attributed to a significant decrease in the charge collection volume with no or minimal decrease in the critical charge.

I guess Xeon and Itanium circuit designers don't have to worry too much about SER for this generation...

Slide 13 shows metal thickness of 22nm interconnect stack.
If we assume width=pitch/2, then upper metal layers have agressive aspect ratio of 2, metal layer M8 is even 2.6.