Intel Corp (INTC)

[jokerman]

good point, maybe in the future it will be integrated on the PCH that uses a more analog friendly process tech.

Actually I think the following partition may make sense for future products:
- main die optimized for logic, containing cores, graphics cores and SRAM cache. (using III-V tunnel transistors or GeSn gate-all-around CMOS). extremely low voltage allows very-low k interconnect. More thick metal layers will be used to allow transmission line interconnect between the cores, solving the RC scaling problem.

- PCH die optimized for analog and eDRAM. PCH will include all IO, even memory IO (!) and a huge eDRAM cache. The eDRAM will ensure that PCH die size is not bump limited.
- main die and PCH die linked by very low power IO (MCP, 2.5D interposer, TSV ?)

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FIVR uses air core inductors, so it's not really magnetics.
My guess is that the high switching frequency (140 MHZ) also helps a lot to reduce the influence of the inductors/capacitors.

Intel has researched CMOS backend magnetic material layers above the metal layers, but now I assume this will not come anytime soon.

Intel claims that HSW FIVR is economically feasible because FIVR can be spread across the main die, using bumps borrowed from neighbouring regions that do not need them.

HSW FIVR has VCCIN at 1.8V. HSW FIVR uses thin-gate transitors in a cascode configuration that allows operation at 2xVMAX.

So for Broadwell I expect higher switching frequencies because of better transistors. (~170 Mhz ?). This will reduce the physical size of the ACIs and also the inductive losses.

VCCIN may drop to 1.6V, but this is ok as the operating voltage is lower as well. If Intel will offer thick gate transistors on their standard CPU process at 14nm, VCCIN could stay at 1.8V. (but maybe backend dielectric reliability is the real problem...)