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What do you think such posts make you?
From my point of view a lot of the pointless debate you had with him was because your view points could not be reconciled. That and because there was no respect for thinking differently.
If so, amazingly, you both have a good chance to get along much better now.
Regards,
Rink
Duke, You're right in what you said about Conroe vs Northwood. It's just that Northwood was my closest comparison, not because of the leap in it's architecture but simply because it put Intel back into the performance lead.
You're wrong in me showing any disdain. I think that AMD's large increase in fab capacity is under-emphasized as I think it is currently the second most important thing for AMD after having a better design would be because it allows AMD to produce much more dual core chips than they'd otherwise could do at 90nm. Similarly in 2007 it'll also allow them to produce bigger higher performing chips than without that big increase in capacity. If my use of English language is what makes you think that I was showing disdain, consider I had to look up both 'snooty' and 'high falutin' in order to know what that meant - English is my second language. I posted reasons for the conclusions I made in that post (it's what I strive to do in general).
You're also wrong in saying that I would have a self-important attitude. I don't. If you'd know me you'd see I'm always open for correction based on solid arguments. In our previous discussion (yesterday or the day before that) I missed your arguments which is why I had no reason to change my opinion. In my social environment (hope I use the right words here) I'm actually known as being one of the first guys to give in provided the arguments are solid. That is because I care about reality and truth more than about being right. This is what I seek here as well because it helps me with my investment decisions.
Regards,
Rink
re: AMD and its camp followers will be singing a different tune all right in a quarter or two. No doubt they will shift the debate from product performance and power efficiency back to the PR lawsuit
Product performance and power efficiency will largely redefine Intel's strengths.
The lawsuit isn't due to finish until 2008/9. It's much too early to have that much influence on the stock.
One thing that I think is under-emphasized though is that AMD this year will increase it's fab capacity quite a bit. This will allow the necessary richer mix of dual core vs single core products, and might allow it to stay afloat much better until the combination of 65nm, SiGe, and K8L (than when this capacity would not be available, like when Northwood started outperforming K7). This presumes that K8L will be up to NGA.
Current rev E&F K8's will be pushed to midrange when comparable NGA parts are launched, and then on to low end. Meanwhile the combination of 65nm and K8L will be introduced somewhat on top of current K8 performance (a bit like Woodcrest/Conroe now but with less of an advantage over previous generation I presume). Timing of 65nm and K8L will be highly important. 65nm looks like it will be shipping in Q4. I presume SiGe between 65nm launch and K8L, and my guess for K8L is that it will more or less make the rumored H1 '07 window, probably Q2-ish.
In short I am currently guessing that end 2007 the situation will be less dire for AMD then it was some 18 months after the launch of Northwood. It's based on quite a bit of presumptions though; it's still a long way out and there isn't a clear enough roadmap from AMD's side.
Regards,
Rink
re: On the flip side though is Spansion into NAND??
Not exactly. They will start shipping ORNAND this summer (Mirrorbit-like NOR with a NAND interface). Different characteristics. Mainly as MCP's containing both Mirrorbit, ORNAND, and some sorts of embedded RAM, and mainly for higher gen cell phones.
Regards,
Rink
AMD socket AM2 etail prices emerge. From €66 for Sempron 64 2800+ to €1223 for FX62. http://www.theinquirer.net/?article=31233
Regards,
Rink
VPro is new name for Intel Pro platform: http://www.theinquirer.net/?article=31191
Intel Pro platform aims at AMD: http://www.theinquirer.net/?article=31204 It won't get into gear until Conroe.
EDIT: Intel goes corporate green. VPro unveiled: http://www.theinquirer.net/?article=31219
Regards,
Rink
HT 3.0 spec released. 42GB/s. 2-32 bits wide. 1.8-2.6GHz. Autosensing short/long distance. Hot plug. Etc...
http://www.hypertransport.org/news/pr/HyperTransport_30_Press_Release.pdf
http://www.hypertransport.org/docs/tech/ht30pres.pdf
"
...
In addition, HyperTransport 3.0 supports a variety of new features including AC
coupling mode, hot plugging, un-ganging mode and dynamic power management for the support
of extended signal transmission distance, typical of backplane and chassis-to-chassis
implementations.
...
HyperTransport 3.0 extends the 1.4 GHz dual data rate (DDR) maximum clock of HyperTransport
2.0 to 1.8 GHz, 2.0 GHz, 2.4 GHz and 2.6 GHz, and delivers a maximum aggregate bandwidth of
41.6 gigabytes per second (GB/s) - a bandwidth increase of 86 percent over HyperTransport 2.0.
...
"
Courtisy of Buggi/SI.
Regards,
Rink
Kate, that may well be the case, but I haven't read most of his posts the last 8 months, he posts a lot, and I can't use search here. I only recently (~ a month ago) started reading more posts here. Even then I've not read every post. As you know I've scaled down AMD pretty far (most of it when it broke $37 in downwards direction) already and am looking for an entry in Intel this Q before Woodcrest launch. I plan to read more, but so far have followed a couple of guys like Chipguy, a couple of others, and some topics that seemed interesting to me.
Regards,
Rink
Duke, you still haven't given a single reason why my logic would be incorrect (US customers buying Japanese products and hence would be effected from limiting AMD's case against Intel to US-only, which likely will prohibit Farnan from granting Intel's motion). Not a single reason, besides some baseless babbling that the law isn't fair.
You claim to have a theory but don't even state WHY that would be more probable to have an effect on the upcoming ruling than what I said. Again no reasons. BTW, besides that 'why' can you give me a link to your theory so I can have a look (I can't use search here).
re: The law is not rational, it is not fair, its reasoning is what is contained in the law. In this case, the law of Antitrust and the "law" of International ("Long Arm") jurisdiction.
Non sense. By FAR most US laws look pretty fair to me (same as in Europe) because it is mostly based on solid reasoning that most people at least consent to, as is perfectly logical in a democracy. In fact if you don't think the same you must have some pretty wild ideas. Again you refrain from giving even a single reason WHY the law wouldn't be more or less fair in this case. That's a bit weak wouldn't you say? It's your claim, so where's your beef?
You apparently can't give reasons or at least don't post them in your replies to me. You can state "You don't have a theory, you have a wish." as long as you want, but if you don't give any direct reasons as to why my logic would be incorrect, or why you think the law will not be fair in this particular case your words can't but sound plain baseless to me.
Regards,
Rink
Duke, no not an attorney. That doesn't mean that what I stated is per definition illogical, does it?
You chose not to react on the contents of my post itself. That's fine of course, but don't you think that it isn't a bit weak at the same time?
Regards,
Rink
Kate, the reason why Intel request to limit the lawsuit case to US only will likely fail imo is because, although misconduct might have taken place in far away Japan, US customers were wronged by it (because they also buy Sony / Tosh / NEC products). Actually I don't see how Intel stands a chance for this particular request.
Regards,
Rink
Mmm, when is Power 6 due?
MORP - Don't think I saw that acronym before.
BTW, as you know I never compare Itanium growth figures to Power but include PA RISC / Alpha / High end MIPS as well because main Itanium growth comes just from replaces those three.
Regards,
Rink
UnD, Wbmw, tx for the correction (eom)
Regards,
Rink
Kate, because all other articles tell a different story. Here's one example. It shows that the motion was Intel's (does not mention Farnan asking for it) + Farnan will decide on May 2 (i.e. he simply hasn't decided yet to speed up the case by limiting it to US only): http://www.extremetech.com/article2/0,1697,1952207,00.asp
Upon announcing it would move to limit the case US only the judge told Intel it's unlikely to be granted unless both parties agree on the facts. Farnan then told Intel to file the motion before May 7: http://www.marketwatch.com/News/Story/Story.aspx?dist=newsfinder&siteid=google&guid=%7B48B58...
Taken together that's exactly what I said.
Regards,
Rink
Kate, my last post on this subject.
re: What do you want? Names? Nafziger was one of SEVERAL lead Itanium designers.
No Naffziger wasn't just one of several leaders of IPF design teams. He lead the teams that did what I think are the most important IPF designs (McKinley and Montecito). From what I read he was the main guy both times. The fact that at that time there were a small hand full of other guys with a similar function (leading teams that did Merced and Madison) is hence imo less relevant.
re: Why is it signifcant? Because you find it so? Did Andy Glew leaving Intel going to AMD and back to Intel REALLY affect Intel or AMD? nope.
Partly answered above. IPF design team leader for McKinley and Montecito is a relevant guy. Apparently he has been trusted and relied upon for crucial designs for a good reason. Also he took a couple of his designers with him.
EDIT: I see Chipguy addressed part of this already. He differs with me in that he says that it might be good for the rest of the 350 people design team as he was responsible too for the slip of Montecito and might therefore have better prospects at AMD than at Intel. Reasonable enough. I still think it's relevant though (Montecito delay is hardly the only thing on his resume).
Regards,
Rink
John, I think that Inq article is wrong. For as far as I read in other articles Intel asked Farnan to dismiss matters that occurred outside the US and Farnan was viewed unlikely to grant that motion.
Regards,
Rink
Kate, you're not being specific enough as you did not react to my main point which is that Sam Naffziger lead both the design team responsible for McKinley, and that for Montecito. Your post actually does not deny this. Sam wasn't just another design team leader which is what you just implied. He lead the teams responsible for what I think were/are the most significant IPF designs (McKinley & Montecito). That is at least what I understood from reading RWT (small article + some PdM posts).
For this board it's not relevant whether you find him having left sad or not; it's a significant departure both for further IPF development and for AMD.
Regards,
Rink
Drjohn, last I heard Turion X2 will be launched May 23, real volume probably start a bit later like in first half of Q3 because it's a socket AM2 processor requiring new mobo's.
Regards,
Rink
Chipguy, you know very well that IPF was chosen to replace PA RISC + Alpha + High end MIPS, that development on those last three architectures ceased at HP and SGI, and that the total market of IPF + PA + Alpha + High end MIPS isn't growing. So the very high Itanium growth rates aren't that impressive considering this.
Montecito will change the equation, meaning even more difficult position for SPARC (this sandwich between POWER+IPF and x86 is getting squeezed and it doesn't look like this will stop until possibly Rock). POWER should be OK though as Montecito does not seem to have a significant enough advantage over POWER to grab significant share from it. x86 server sales won't see current long term revenue growth getting curbed as a result of Montecito. Just my 2c.
Regards,
Rink
Kate, The main one for McKinley and Montecito (the two most relevant Itanium chips imo). Sam Naffziger, previously from HP. That's at least what I recall from reading RWT.
Regards,
Rink
Wbmw, re: saying that the downward guidance takes into account a week or two of OEM inventories that need to be burned off... in the third quarter, right? I thought I heard they guided inventory up slightly for the second quarter. Not entirely sure.
In hindsight I might have missed a buying opportunity last couple of days. OTOH they're scaling down share buy backs in Q2 to half of the value they spend in Q1. So it's not impossible that we might touch $19 again. Still the closer we get to Conroe/Woodcrest the smaller the chance that this will happen.
Also with Conroe ramping to 40% of the DT mainstream + performance segments in Q1/07 (source: Anandtech, slide excluded value segment), there's plenty of opportunity for AMD to sell A64 X2 in the mainstream market just below top end Conroe. They sure have sufficient capacity for it by then even at 90nm. So I think taking back unit and $$ share will be a relatively gradual thing turning into more serious share gains towards ~Q1/07.
Server is a slightly different story. I think as soon as Woodcrest hits the market it'll turn out pretty hard for AMD to convert more customers. AMD will probably keep selling very nicely to their current customer base until Woodcrest has ramped to a similar 40% of server processor units, at which time some current AMD customers will probably walk right back to Intel.
The best thing for Intel that I heard on the call was that Merom apparently will be launched in Q3 as well, in time for xmas shopping. That for me is reasonably significant.
NGA should be a block buster success but it needs ramping to gain back overall market share. As a result 3rd quarter guidance might not yet reflect significant $ share gains (Netburst will sell at even lower prices while NGA will about make up for that).
Just my 2c.
Regards,
Rink
Right now (AH) the market focuses on the positives and is up ~2%. Just a moment in time of course...
Regards,
Rink
Intel Q1 net earns 23c
Intel Q1 rev $8.94B
Intel Q1 First Call earns est 23c
Intel Q1 First Call rev est $8.91B
Intel Q1 gross margin 55.1%
- MarketWatch.com
______________________
Key Product Trends (Sequential)
Total microprocessor units were lower. The average selling price (ASP) was slightly lower.
Chipset, motherboard and flash memory units were lower.
Application processor units for products such as cellular phones and PDAs were lower.
http://biz.yahoo.com/bw/060419/20060419005903.html?.v=1
_______________________
Q2 2006 Outlook !!!
Revenue: Expected to be between $8.0 billion and $8.6 billion, below normal seasonal patterns. The company believes PC growth rates have moderated in recent quarters, resulting in above-normal customer inventory levels that are limiting demand in the short term.
Gross margin: 49 percent, plus or minus a couple of points (50 percent, plus or minus a couple of points, excluding share-based compensation effects of approximately 1 percent).
___
Regards,
Rink
Wouter, re: It's right there in the article :)
Right... I saw the original presentation that contained that slide, and I thought it signified that fab 36 would be 'fully converted' (and I still think so). Fab 30 wasn't scheduled to convert, not until at least much later. So 'fully converted' refers to fab 36 alone. 'Substantially converted' in my opinion so far refered to the output fab 30 + fab 36 combined. I could be wrong ofcourse but that's how I see it.
Regards,
Rink
Kate, re: AMD fab capacity.
Another article confirming his doubtful reputation.
They had a little gathering to talk about it, and as we greatly suspected, said nothing more about 65nm conversion than they have in the past. Indeed, if anything they indicated a bit of a delay, now saying that 65nm conversion will be "substantially" rather than "completely" converted to 65nm by the middle of 2007.
AMD always said it would be 'substantially converted to 65nm' by mid 2007 because fab 30 will keep producing 90nm chips and won't be converted to 65nm. There isn't a single quote that I'm aware of that AMD claimed it would be fully converted to 65nm by mid 2007.
What they don't explain is why AMD outsourced production to Chartered rather than convert Fab 30 to 65nm. Obviously, Chartered isn't doing this for nothing.
The only conclusion one can reasonably draw from this is that AMD couldn't afford to build Fab 36 and convert Fab 30, so they'll pay Chartered extra for some extra capacity.
Nah. Fab 30 was made for 180/130/90nm. As I understood it the conversion to 65nm is non trivial for this particular facility (will require more changes and hence more resources, time, and space than previous conversions in that facility). Consequently, even if more fab capacity would not have been needed AMD hardly had a choice but to build a new fab (fab 36).
Chartered's fab 7 only provides the flex capacity in that chart that Ed copied; fab 7 isn't only producing for AMD. In case AMD uses fab 7 it runs it's own facilities at close to 100% capacity (and hence maximizing profits from it). Flex capacity from Chartered will no doubt be profitable as well (as otherwise there is no reason to use it). I think this is a very sound business model for AMD.
So instead of Stroligo's "only reasonable conclusion" I think that it's more reasonable that it's just economically more sound for AMD (considering both costs and risks) to use Chartered than to convert fab 30 to 65nm and use the additional capacity from the shrink for flex purposes. Stroligo's singular conclusion that AMD isn't capable of raising the required money is narrow minded and not supported by any evidence. The fact that he is 'able' to conclude that it's the only possible conclusion is telling. The first step towards wisdom is to know there's simply a heck of a lot you don't know.
In case you disagree I'd appreciate to see the reasons why.
Regards,
Rink
Conroe performance claim being busted: http://sharikou.blogspot.com/
Some conclusions on Aces:
Redpriest: "Conroe can only read 1 128-bit load per cycle."
Eric Bron: "ah yes, that's why I was thinking from your comment that some of your tests were read only, anyway the L1 write bw is fabulous when compared with the one in P4, welcome back the writeback L1 !
the balanced L1 R/W bw (+ mem disambiguation) should have a big impact on algorithm design, instead of avoiding stores we will be allowed to do more creative things."
Link for above quotes: http://www.aceshardware.com/forums/read_post.jsp?id=115160675&forumid=1
It's a bit weird to read that Conroe might only be able to do one 128b load per cycle as an Intel presentation claimed it could execute several 128b ops simultaneously.
Also Conroe performance might improve a lot in a limited amount of sub benches when Intel's compiler is modified for it.
Regards,
Rink
Wouter, tx! (eom)
Wouter, tx.
I'd like to add that I read several articles that SiGe will be used in rev F at 90nm already (IBM/AMD developed SiGe induced strain for 65nm but AMD chose to retrofit it's 90nm process with this technology while IBM chose to introduce it together with it's 65nm process as originally planned). So we should see the results of the additional 15% relatively shortly.
Just to refresh my own memory: One of those articles mentions "The PMOS devices now run almost as fast as the NMOS transistors. Wei said the new process will allow design engineers to better balance the size of the N- and PMOS transistors to achieve performance improvements at the product level that he said could approach 50 percent." ('approach 50%' probably is the same as the 42% you mentioned when compared to bulk, i.e. 15% or so more than with the previous version of strain): http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=174901200 Combjelly added some comments to this article a while ago at ihub saying that it leads to significantly smaller PMOS transistors: http://www.investorshub.com/boards/read_msg.asp?message_id=8768792 I wonder if this might be the main reason why the L2 cache could be shrunk as much as was shown in the 65nm die photo, and might be one of the reasons why Intel's current L2 cache is so much denser than AMD's current L2 cache.
It's interesting that you say that first 65nm products will not use SiGe for additional strain, and that it will be integrated in the process early '07.
Regards,
Rink
"AMD promised a 40% increase in transistor performance with the 65nm conversion."
Note: Not much other news in that article that hasn't been talked about already (2nd article on the page). Here's the link: http://www.notebookreview.com/default.asp?newsID=2873
Wouter, do you know if AMD has said anything during that München meeting about this?
Regards,
Rink
[Cray's] Cascade will be implemented as a series of steps. We currently support varied computing needs with a set of individually architected machines. In 2007, our follow-on machines [i.e. vector/Cray, scalar/AMD, FPGA/Xilinx] will be coupled together, creating a unified user environment and file system with the ability to launch applications on different processor types. [I'm guessing that the recently announced 1PFLOP 24K processor system, code name Baker, in 2008, mainly examplifies the scalar part of this. It's an intermediate step towards a larger goal:] The Cascade system, to be prototyped in 2010, will tightly integrate all the processing technologies into a single system and provide the adaptive software to make the underlying heterogeneous processing transparent to the user.
http://www.hpcwire.com/hpc/614695.html
The words in between brackets above are mine. Do feel free to put me straight if I miss something important.
BTW, I guess this means that the Adams code name I heared previously might relate to the vector part. Together with Baker they might make up / evolve into Cascade.
Regards,
Rink
Hans de Vries states the 65nm die photo on Tweaker.net shows a chip that is essentially the same as a rev F: 3-way K8 with much denser L2.
http://www.realworldtech.com/forums/index.cfm?action=detail&PostNum=4254&Thread=6&entryI...
http://www.realworldtech.com/forums/index.cfm?action=detail&PostNum=4254&Thread=9&entryI...
Regards,
Rink
DJ Market Talk: Advanced Micro Inventory Said To Be Growing
(call: 201 938 5171; e-mail:john.shipman@dowjones.com)
MARKET TALK can be found using N/DJMT
10:59 (Dow Jones) Advanced Micro (AMD) is seeing inventory grow, says
ThinkEquity's Eric Ross. Asian distributors are saying supplies of AMD chips
have "loosened up," he says, which marks a change from a month ago when there
was almost zero inventory. "In some cases inventories of these parts seem to
be building more than expected," Ross adds. "As much as several weeks or more
have built up in many products, according to our checks." He says AMD is
offering discounts to reduce the inventory. Shares off a fraction at $34.71.
(DLF)
__________________
My take is that AMD parts supply has become better and some distributers and OEMs took the opportunity to increase inventory to more normal levels (almost zero isn't normal).
Regards,
Rink
Wouter, I didn't know you wrote for Tweakers.net, until this article about the AMD München press meeting that showed it's progress with fab 36 and process development.
I took the liberty to translate some of it over here: http://www.siliconinvestor.com/readmsg.aspx?msgid=22331262
Regards,
Rink
Alan, My take on the AMD 45nm news...
I think it was more of a:
"We built a 45nm SRAM"
Rather than a
"We built a 45nm SRAM, and it works"....
There is a world of difference between those two statements.
could be wrong though... we will see.
Agree. Still I don't think AMD would show a completely non functional 45nm test wafer. I guess at least some of the test SRAM is functional.
Regards,
Rink
Wbmw, re: My guess is that they taped out in January and got the wafers back the day before yesterday.
Isn't it three months from wafer start to packaged product (meaning less than that just from wafer start to wafer finish)?
Regards,
Rink
Conroe Dhrystone of 28742
http://vic.expreview.com/attachment/sis+alu.jpg
http://vic.expreview.com/attachment/sis+cache.jpg
http://vic.expreview.com/attachment/sis+media.jpg
http://vic.expreview.com/read.php?1
Above's courtisy of Mas on the AMD thread.
Regards,
Rink
(deleted; not relevant; tx Wouter)
(irralevant as Wouter shows in the next post)
Wbmw, Zetopan, tx for some clarity about Super Pi.
Rergards,
Rink
Duke, yep, that's why I wrote 'VERY exciting conf call' with the first word in capital letters.
Regards,
Rink