Intel Corp (INTC)

[Ixse]

Wouter, tx.

I'd like to add that I read several articles that SiGe will be used in rev F at 90nm already (IBM/AMD developed SiGe induced strain for 65nm but AMD chose to retrofit it's 90nm process with this technology while IBM chose to introduce it together with it's 65nm process as originally planned). So we should see the results of the additional 15% relatively shortly.

Just to refresh my own memory: One of those articles mentions "The PMOS devices now run almost as fast as the NMOS transistors. Wei said the new process will allow design engineers to better balance the size of the N- and PMOS transistors to achieve performance improvements at the product level that he said could approach 50 percent." ('approach 50%' probably is the same as the 42% you mentioned when compared to bulk, i.e. 15% or so more than with the previous version of strain): http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=174901200 Combjelly added some comments to this article a while ago at ihub saying that it leads to significantly smaller PMOS transistors: http://www.investorshub.com/boards/read_msg.asp?message_id=8768792 I wonder if this might be the main reason why the L2 cache could be shrunk as much as was shown in the 65nm die photo, and might be one of the reasons why Intel's current L2 cache is so much denser than AMD's current L2 cache.

It's interesting that you say that first 65nm products will not use SiGe for additional strain, and that it will be integrated in the process early '07.

Regards,

Rink