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simplytom

02/11/14 5:28 PM

#129624 RE: This Causes an Error #129623

Ahh, fair enough. You're right. Maybe they weren't as aggressive because they had expected CLT+ to be more competitive than it turned out to be, so they have only recently begun to lower prices on those chips?



They lowered the prices this year.
Because they want to hit the 50Million Tablets in 2014.
BK never mentioned which soc is sitting in those 50 Million devices.
I'm quite convident that they will overdeliver this number.

Just for the record.
A clovertrail+-tablet is stronger in both gpu and cpu then a Kindle fire hd 7 and a Samsung galaxy tab 3 7inch.

Both (kindle and sgtab3-7) are volume models.

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wbmw

02/11/14 5:51 PM

#129627 RE: This Causes an Error #129623

Remember, we're talking about what is very likely a 100mm^2 die being sold for maybe $10 tops.


Again, on Intel's 32nm process, which began its ramp in 2007, about the same time TSMC was kickstarting 40nm. Any idea how cheap those wafers are, more than 6 years later...?

You are overly focused on die size, when silicon cost is a function of both die size as well as wafer pricing. And wafer pricing is a function of yield, maturity, throughput time, metal layers, and many other vectors.

While I wouldn't be surprised to see the pricing around $10-15 for the SOC (the pricing is a function of the system level price, which is driven by market demand and economics) - don't forget that Intel has to sell ABOVE COST, meaning that they can manufacture a 100mm2 die on this process node for even LESS.

Rather than being the armchair expert who pretends to know Intel's cost better than they do, just look at anecdotal evidence to see the kinds of system prices they are already targeting, which should tell you a lot about their cost structure, even in spite of the large-ish die.