Replies to post #3303 on Advanced Micro Devices Inc (AMD)

[kpf]

fyodor re: Cache density

The difference of cache density between Opteron and Tbred cannot be explained by way-ness of cache as they are run the same way as I learned today. But easily to explain from a mature bulk-process for the latter and a juvenile SoI-process for the Opteron.

As for Banias, the diesize is not from speculation but from some Intel-document posted here, so that should be solid.
As for the comparison of Banias and Barton it is a lot more than 30% because Banias has 1MB L2 and Barton just 512KB of it.
Ok there is 128KB L1 for Barton as well compared to just few KB L1 for Banias as well. But sums up for roughly twice the cache density for Banias compared to Barton.

Just curious where it comes from. Some speculation here and there is that Intel runs its L2-caches at half CPU-speed and twice the bandwidth or so (if I understood that right). No clue at all about neither if this is possible nor if it applies indeed.

However, thanks again for sharing your knowledge.

Klaus

[Dan3]

Re: die size for Banias

82.8 mm2 according to Intel Docs.

Look on page 45 of http://developer.intel.com/design/mobile/datashts/25261201.pdf where the die length and width are given.

Edit: I see that's already been posted.

Given that Pentium III-M on .13, with half as much L2 and no SSE2, was about the same size, it's reasonable to assume that they've used some (or much) of their 90nm process technology to produce the chips.