Replies to post #119934 on Intel Corp (INTC)

[Golfbum]

I can't wait for the 14nm ramp at Intel to lay waste to all the dreams of others...

gb

[mas]

Interesting technical article. Obviously this is the battle for the foundry's next premier process and having a proper 14nm process might just help FD-SOI get some traction over all the hybrid 14/16-20nm Bulk Finfet processes planned by TSMC and Samsung with Globalfoundries being the potential beneficiary if FD-SOI is as good as Asenov claims although he has been known to be biased in his past pronouncements ;-).

There has been a dual-core 2.5 GHz A9 released at 28nm FD-SOI which is the fastest A9 released so far.

http://www.eetimes.com/design/communications-design/4404445/ST-Ericsson-shows-FDSOI-smartphone-processor-

ST Micro are releasing a dual-core A15 with Power VR6 next.

[chipguy]

This prof has a history of being a sock puppet for the SOI related
support industry.

The great battle between Intel and IBM for the future of semi process
technology? Does anyone buy that story line after IBM's waterloo on
the plains of hk/mg? :-D

[wbmw]

Under the $100 billion Places2Be programme announced by EU vice president Neelie Kroes last month, the EU is putting up €360 million to support FD-SOI manufacturing in Dresden and Crolles. Half of ST’s R&D budget – some $300 million – will also be going to support the FD-SOI development.

This is really just a drop in the bucket, and potentially money wasted if FD-SOI isn't the right direction. That's the way research goes... you invest, and then see 5-10 years later if the investment pays off. Very rarely, it pays off big. Most commonly, it's a sunk cost.

Intel hasn’t said why it went for the trapezoidal shape but Asenov has some ideas

You mean they don't know yet? They're still guessing at this point?? Man, they are behind!

“Compared to a rectangular fin, Intel’s trapezoidal fin delivers 15% less performance for the equivalent height and width,” says Asenov.

However, IBM, by using SOI finfet, has shown it can get closer to the ideal rectangular shape.

I don't see how they could come to this determination, without having access to the process and the conditions to set up a real experiment between both structures. Reminds me of when IBM claimed that gate-first HKMG were superior to Intel's gate-last approach. Then the industry started building gate-first, and realized that the yields were poor, and they still aren't producing 28nm parts in volume.

“We must be ready with 14nm FD-SOI before anyone has finfet at 14nm,” says Chery.

Sure. Good luck with that! :-)