Replies to post #66825 on Advanced Micro Devices Inc (AMD)

[chipguy]

One item that hasn't seemed to have been noted by anyone is that the 3800 X2 used in the Anandtech review has only half the total L2 cache of the Yonah, so the IPC is actually skewed in AMD's favor even more than suggested. We'd see this if it were possible to compare using AMD's 1MB L2 dualcores at 2.0 Ghz. For instance when running single threaded apps such as Doom 3, Yonah's shared cache 2MB is running against the 3800 X2's 512KB per single thread--four times the cache on Intel's side is required to get close to AMD in fps.

AMD *chose* to use up K8 die space to integrate a bunch
of northbridge functions *instead* of bigger L2 cache(s).
That is a basic architectural tradeoff. Even with its 2MB L2
Yonah is a small (91 mm2) device made in bulk CMOS with
relatively few layers of interconnects. It is likely dirt cheap to
manufacture yet offers dual cores with great performance
at very modest power. Small wonder Apple is moving away
from PowerPC to Intel processors.

[wbmw]

Re: One item that hasn't seemed to have been noted by anyone is that the 3800 X2 used in the Anandtech review has only half the total L2 cache of the Yonah

You're forgetting that the die size for Yonah is only ~90mm^2, which is less than half the size of a 2x1M X2 processor. AMD has to ramp their 2x512K cache dual cores; otherwise they would not be able to meet capacity demands.

Re: For instance when running single threaded apps such as Doom 3, Yonah's shared cache 2MB is running against the 3800 X2's 512KB per single thread--four times the cache on Intel's side is required to get close to AMD in fps.

Maybe as an academic experiment, you can try to create a system with 512KB Yonah CPU and an Athlon X2 that accesses memory from off of a Northbridge (as opposed to the integrated memory controller), and then see how the two perform. But for real world scenarios, you're going to have to accept the fact that Intel can integrate more L2 cache in a smaller area, while AMD chose to integrate their memory controller for higher performance.