Replies to post #57933 on Advanced Micro Devices Inc (AMD)

[chipdesigner]

I don't interpret his statement to mean "already updated", but rather that he wouldn't be surprised if it were *to be* updated for QC Opteron. (by which he is joking, hence the smiley, since it has to be updated for (true) QC to work.)

But we should probably stop all this discussion of QC Opteron coming in early 2006. It makes wbmw and the other Intel acolytes very nervous.

[jhalada]

Rink,

my reading of that post is the same as chipdesigner's, I don't agree with Petz's interpretation.

Joe

[jhalada]

Rink,

While on subject of QC, Socket F and need for additional bandwidth (and use of pins to do so). A random thought occured to me that would make a lot more sense than doubling the width, and it would improve performance greatly as well.

I think AMD should add 4th HT link, and maintain the same width.

Consider a 4 way system, where 2 links are used to other processors, 1 for I/O. Now compare it with a system where 1 link is used for I/O, and 3 links to attach to other 3 processors.

The advantages are as follows (assuming the speed of the link is the same):
1. Interprocessor communication bandwidth goes up by 50% - from 2 to 3 links
3. The amount of trafic goes down by 25%. Wheras to send 1 pocket to each of the 3 processors cost 4 segment worth of traffic (2 x 1 hop, 1 x 2 hop), with 3 links it is only 3 (3 x 1 hop)
3. Latency is reduced to 1 hop

The increase of pins needed by HT is 33%, but the benefit is far exceeding 33%

Similar benefits would occur in systems extending 4 sockets (although I think the volume of those will go down from low to very low when QC become available).

Joe