Replies to post #4642 on Transmeta (Semiconductor) (TMTA)

[sf_tal]

Disclaimer for Industry Wide Flaw Post

I should mention that I transferred his post over from another board,Yahoo, where I believe I made it abundantly clear that I was asking questions and for opinions from engineers and people knowledgable about chip architecture.

I assumed that people on this board would know from prior posts I made that I am not any of that, and just making surmises.

In other words, I was/am asking questions if my ideas about the inner workings of the two chips, Intel based, or Transmeta's emulated version (sort of holographic, in my mind), are correct.

And of course, by referring to the Centrino as an ocutupus playing patty cake, I in no way meant to be derogartory, but was just conlcuding my post based on my hypothetical questioning and analogies, and do not mean to imply, that with their 30,000 engineers, this is a problem they can't fix.

In other words, my post was meant as a series of questions, not as assertions. No offense to the Centrino, which I believe is a very good chip, even a brilliant one.

_tal :-)

[wbmw]

tal, Re: <<Intel's processors use power-management techniques such as throttling back the clock speed or shutting down portions of the chip when those areas or transistors are not required by a particular instruction stream. When the chip does this, it puts the memory module into what is called self-refresh mode, Kasik says. The memory chip can move into or out of this state thousands of times a second, he says.>>

Wow! It would seem to me purely from the lay observor's perch that Intel may have a problem here that Transmeta might not.

The above is not specific to Intel. Self refresh mode is something that any chipset will activate (including integrated ones) when they go into low power mode. First, let me give you some basic understanding of DRAM.

DRAM is made from transistors and capacitors. The capacitor holds a charge, while the transistor acts as a switch. When a device reads a bit from memory, the transistor will allow the charge to travel to the sense amps, which will read the information as a '1' or '0'. The problem with holding charge in a capacitor, however, is that capacitors leak over time, and within milliseconds, the charge will be gone and data will be wiped clean from memory.

In order to prevent this from happening, there are commands known as "refreshes", which recharge the DRAM at regular intervals to maintain the data integrity. Usually, the chipset controls how often these refreshes go out. This is necessary because refreshes cannot conflict with memory reads or writes, or else the data can be corrupted. Complex logic within the chipset can determine how to keep accurate timings.

However, when a chipset enters sleep states, it also shuts off its refresh functionality to save additional power. Since turning off refreshes means that the DRAM will lose its contents, the chipset will put the DRAM into a "self refresh" mode, which means that small devices on the DIMMs will refresh the DRAM automatically. Since the chipset is in a sleep state, there will be no read or write conflicts, so it's allowable to do this.

If the self refresh logic has a bug, it's possible that the DRAMs may not get refreshes at the proper intervals, and the system can lose important data. However, this will be the case with any CPU or chipset that goes into low power modes. The DRAM needs refreshes one way or another, even if there is a Transmeta CPU instead of an Intel one.