Keith,
There was also the suggestion that removing the 2 HT links and some other minor optimizations would allow Winchester to be a 1MB L2 cache part @ 102mm^2. Considering what INTEL has in the pipeline against Winchester, that might turn out to be necessary.
Well, Dothan will have 2 MB of L2 and so will I believe Tejas.
No matter how low the latency of memory is on K8, at some point, in certain apps, the size of L2 will overwhelm the on die memory controller, if the AMD CPU;s L2 is too small.
Regarding the HT links, do you know if all 3 links are active in current K8 processors? For example, if a mobo supplier chose to have both AGP and PCI-X, would it be possible to attach each to its own link?
Joe
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