"the difference between Winchester and San Diego seems to be only 12mm^2"
Hmm, that implies 1M of L2 cache occupies 24 mm^2. At 130nm, given that Newcastle is supposed to be about 150 mm^2, 1M of L2 cache is about 84 mm^2. Ok, so maybe AMD solved their apparent problem with the proportionately large size of their L2 caches. But that would mean the CPU plus L1 caches has only gone from about 109 mm^2 at 130nm to about 90 mm^2 at 90nm. Somehow, I expected more. Even if they stripped out the extra two HTT ports for Newcastle, I expected more. Maybe HTT ports take more die space than I expected.
Or maybe 90nm is more than just a straight shrink. Stranger and stranger...
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