CG, do you know how much power the MCH in the Montecito platform consumes? If intel further consolidates the south and north bridge into a single chipset, then Tukwila's system level TDP may be comparable to Montecito's.
What you are saying is that greater activity will bite you with greater power dissipation. Energy dissipation per activity stays almost constant. Better design and process technologies will improve that number somewhat.
That implies that the Nehalem clock frequency may not be that great because of the greater activity under peak conditions.So it is imperative that the clock frequency is adjusted automatically depending on the work load. Better circuit design techniques are obviously needed even with HiK gates.
There will be no free lunch because the power dissipation will get you. The power dissipation continues to erect speed bumps once again.
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